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ps029902-0212 preliminary copyright ?2012 zilog ? , inc. all rights reserved. www.zilog.com product specification z8051 series 8-bit microcontrollers z51f3220
ps029902-0212 p r e l i m i n a r y z51f3220 product specification ii do not use this product in life support systems. life support policy zilog?s products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) are intended for surgical impl ant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2012 zilog, inc. all rights reserved . information in this pu blication concerning the devices, applications, or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. z8051 is a trademark or registered trademark of zilo g, inc. all other product or service names are the property of their respective owners. warning:
ps029902-0212 p r e l i m i n a r y revision history z51f3220 product specification iii revision history each instance in this document?s revision history reflects a change from its previous edi- tion. for more details, refer to the corresponding page(s) or appropriate links furnished in the table below. date revision level description page feb 2012 02 removed references to 28-pin sop package. all jan 2012 01 original zilog issue. all
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 1 table of contents 1. overview ................................................................................................................... ............................................ 10 1.1 description ............................................................................................................... ...................................... 10 1.2 features .................................................................................................................. ....................................... 11 1.3 ordering information ...................................................................................................... ................................ 12 1.4 development tools ......................................................................................................... ............................... 13 2. block diagram .............................................................................................................. ........................................ 16 3. pin assignment ............................................................................................................. ........................................ 17 4. package diagram ............................................................................................................ ..................................... 19 5. pin description ............................................................................................................................... ....................... 21 6. port structures ............................................................................................................ .......................................... 26 6.1 general purpose i/o port .................................................................................................. ............................ 26 6.2 external interrupt i/o port .............................................................................................................................. 27 7. electrical characteristics ................................................................................................. ..................................... 28 7.1 absolute maximum ratings .................................................................................................. ......................... 28 7.2 recommended operating conditions .......................................................................................... ................. 28 7.3 a/d converter characteristics ............................................................................................. .......................... 29 7.4 power-on reset characteristics ............................................................................................ ....................... 29 7.5 low voltage reset and low voltage indicator characteristics ............................................................... ..... 30 7.6 high internal rc oscillator characteristics ............................................................................... .................... 31 7.7 internal watch-dog timer rc oscillator characteristics .............................................................................. 31 7.8 lcd voltage characteristics ............................................................................................... .......................... 32 7.9 dc characteristics ........................................................................................................ ................................. 33 7.10 ac characteristics ....................................................................................................... ................................ 35 7.11 spi0/1/2 characteristics ................................................................................................. ............................. 36 7.12 uart0/1 characteristics .................................................................................................. ........................... 37 7.13 i2c0/1 characteristics ................................................................................................... .............................. 38 7.14 data retention voltage in stop mode ...................................................................................... ................... 39 7.15 internal flash rom characteristics ....................................................................................... ...................... 40 7.16 input/output capacitance ................................................................................................. ........................... 40 7.17 main clock oscillator characteristics .................................................................................... ...................... 41 7.18 sub clock oscillator characteristics ..................................................................................... ...................... 42 7.19 main oscillation stabilization characteristics ........................................................................... .................. 43 7.20 sub oscillation characteristics .......................................................................................... .......................... 43 7.21 operating voltage range .................................................................................................. .......................... 44 7.22 recommended circuit and layout ........................................................................................... ................... 45 7.23 typical characteristics .................................................................................................. .............................. 46 8. memory ..................................................................................................................... ............................................ 49 8.1 program memory ............................................................................................................ ............................... 49 8.2 data memory ............................................................................................................... .................................. 51 8.3 xram memory ............................................................................................................... ............................... 53 8.4 sfr map ................................................................................................................... ..................................... 54 9. i/o ports .................................................................................................................. .............................................. 63 9.1 i/o ports ................................................................................................................. ........................................ 63 9.2 port register ............................................................................................................. ..................................... 63 9.3 p0 port ................................................................................................................... ........................................ 65 9.4 p1 port ................................................................................................................... ........................................ 67 9.5 p2 port ................................................................................................................... ........................................ 69
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 2 9.6 p3 port ................................................................................................................... ........................................ 70 9.7 p4 port ................................................................................................................... ........................................ 71 9.8 p5 port ................................................................................................................... ........................................ 72 9.9 port function.............................................................................................................. .................................... 73 10. interrupt controller ...................................................................................................... ........................................ 82 10.1 overview ................................................................................................................. ..................................... 82 10.2 external interrupt ....................................................................................................... .................................. 83 10.3 block diagram ............................................................................................................ ................................. 84 10.4 interrupt vector table ................................................................................................... ............................... 85 10.5 interrupt sequence ....................................................................................................... ............................... 85 10.6 effective timing after controlling interrupt bit ......................................................................... ................... 87 10.7 multi interrupt .......................................................................................................... ..................................... 88 10.8 interrupt enable accept timing ........................................................................................... ........................ 89 10.9 interrupt service routine address ........................................................................................ ...................... 89 10.10 saving/restore general-purpose registers ................................................................................ ............. 89 10.11 interrupt timing ............................................................................................................................... ........... 90 10.12 interrupt register overview ............................................................................................. .......................... 90 10.13 interrupt register description .......................................................................................... .......................... 92 11. peripheral hardware ............................................................................................................................... ............ 99 11.1 clock generator ............................................................................................................................... ............ 99 11.2 basic interval timer ..................................................................................................... .............................. 102 11.3 watch dog timer .......................................................................................................... ............................. 105 11.4 watch timer............................................................................................................... ................................ 108 11.5 timer 0 .................................................................................................................. ..................................... 111 11.6 timer 1 .................................................................................................................. ..................................... 120 11.7 timer 2 .................................................................................................................. ..................................... 130 11.8 timer 3, 4 ............................................................................................................... .................................... 141 11.9 buzzer driver ............................................................................................................ ................................. 170 11.10 spi 2 ................................................................................................................... ..................................... 172 11.11 12-bit a/d converter .................................................................................................... ........................... 178 11.12 usi0 (uart + spi + i2c) ................................................................................................. ....................... 185 11.13 usi1 (uart + spi + i2c) ................................................................................................. ....................... 222 11.15 lcd driver .............................................................................................................. ................................. 260 12. power down operation ...................................................................................................... .............................. 272 12.1 overview ................................................................................................................. ................................... 272 12.2 peripheral operation in idle/stop mode ................................................................................... ............ 272 12.3 idle mode ................................................................................................................ ................................. 273 12.4 stop mode ................................................................................................................ ............................... 274 12.5 release operation of stop mode............................................................................................ ................ 275 13. reset ..................................................................................................................... ......................................... 277 13.1 overview ................................................................................................................. ................................... 277 13.2 reset source ............................................................................................................. ................................ 277 13.3 reset block diagram ... ................................................................................................... ........................ 277 13.4 reset noise canceller .................................................................................................... ........................ 278 13.5 power on reset ............................................................................................................................... ........ 278 13.6 external resetb input .................................................................................................... ......................... 281 13.7 brown out detector processor ............................................................................................. ..................... 282 13.8 lvi block diagram ........................................................................................................ ............................. 283 14. on-chip debug system ...................................................................................................... .............................. 287 14.1 overview ................................................................................................................. ................................... 287 14.2 two-pin external interface ............................................................................................... ......................... 288 15. flash memory .............................................................................................................. ..................................... 293
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 3 15.1 overview ................................................................................................................. ................................... 293 16. configure option .......................................................................................................... .................................... 304 16.1 configure option control ................................................................................................. .......................... 304 17. appendix .................................................................................................................. ...................................... 305
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 4 list of figures figure 1.4 standalone gang8 (for mass production) ............................................................................. .. 15 figure 2.1 block diagram ...................................................................................................... .................... 16 figure 3.1 z51f3220 44mqfp-1010 pin assignment .............................................................................. 1 7 figure 3.2 z51f3220 32sop pin assignment ...................................................................................... .... 18 figure 4.1 44-pin mqfp package ................................................................................................ ............. 19 figure 4.2 32-pin sop package ................................................................................................................ 20 figure 6.1 general purpose i/o port ........................................................................................... .............. 26 figure 6.2 external interrupt i/o port ........................................................................................ ................ 27 figure 7.1 ac timing .......................................................................................................... ....................... 35 figure 7.2 spi0/1/2 timing .................................................................................................... .................... 36 figure 7.3 waveform for uart0/1 timing characteristics ....................................................................... 37 figure 7.4 timing waveform for the uart0/1 module ............................................................................. 37 figure 7.5 i2c0/1 timing ...................................................................................................... ..................... 38 figure 7.6 stop mode release timing when initiated by an interrupt ...................................................... 39 figure 7.7 stop mode release timing when initiated by resetb .......................................................... 39 figure 7.8 crystal/ceramic oscillator ......................................................................................... ............... 41 figure 7.9 external clock ........................................................................................................................... 41 figure 7.10 crystal oscillator ................................................................................................ .................... 42 figure 7.11 external clock..................................................................................................... .................... 42 figure 7.12 clock timing measurement at xin ................................................................................... ..... 43 figure 7.13 clock timing measurement at sxin .................................................................................. .... 43 figure 7.14 operating voltage range ........................................................................................... ............ 44 figure 7.15 recommended circuit and layout .................................................................................... ..... 45 figure 7.16 run (idd1 ) current ............................................................................................... ............... 46 figure 7.17 idle (idd2) current ............................................................................................... ................ 46 figure 7.18 sub run (idd3) current ............................................................................................ ........... 47 figure 7.19 sub idle (idd4) current ........................................................................................... ........... 47 figure 7.20 stop (idd5) current ............................................................................................... .............. 48 figure 8.1 program memory ..................................................................................................... ................. 50 figure 8.2 data memory map .................................................................................................... ................ 51 figure 8.3 lower 128 bytes ram ................................................................................................ .............. 52 figure 8.4 xdata memory area .................................................................................................. ............. 53 figure 10.1 external interrupt description .................................................................................... ............. 83 figure 10.2 block diagram of interrupt ...................................................................................................... 84 figure 10.3 interrupt vector address table .................................................................................... .......... 86 figure 10.4 effective timing of interrupt enable register .................................................................... ... 87 figure 10.5 effective timing of interrupt flag register ............................................................................. 87 figure 10.6 effective timing of interrupt ..................................................................................... .............. 88 figure 10.7 interrupt response timing diagram ................................................................................. ..... 89 figure 10.8 correspondence between vector table address and the entry address of isp .................. 89 figure 10.9 saving/restore process diagram and sample source ......................................................... 89 figure 10.10 timing chart of interrupt acceptance and interrupt return instruction ............................... 90 figure 11.1 clock generator block diagram ..................................................................................... ........ 99 figure 11.2 basic interval timer block diagram ................................................................................ ..... 102
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 5 figure 11.3 watch dog timer interrupt timing waveform ..................................................................... 105 figure 11.4 watch dog timer block diagram ..................................................................................... .... 106 figure 11.5 watch timer block diagram ................................................................................................. 108 figure 11.6 8-bit timer/counter mode for timer 0 .............................................................................. ... 112 figure 11.7 8-bit timer/counter 0 example ..................................................................................... ....... 112 figure 11.8 8-bit pwm mode for timer 0 ........................................................................................ ........ 113 figure 11.9 pwm output waveforms in pwm mode for timer 0 ........................................................... 114 figure 11.10 8-bit capture mode for timer 0 ................................................................................... ....... 115 figure 11.11 input capture mode operation for timer 0 ........................................................................ 116 figure 11.12 express timer overflow in capture mode ......................................................................... 1 16 figure 11.13 8-bit timer 0 block diagram ...................................................................................... ........ 117 figure 11.14 16-bit timer/counter mode for timer 1 ............................................................................ . 121 figure 11.15 16-bit timer/counter 1 example ................................................................................... ..... 121 figure 11.16 16-bit capture mode for timer 1 ........................................................................................ 122 figure 11.17 input capture mode operation for timer 1 ........................................................................ 123 figure 11.18 express timer overflow in capture mode ......................................................................... 1 23 figure 11.19 16-bit ppg mode for timer 1 ...................................................................................... ....... 124 figure 11.20 16-bit ppg mode timming chart for timer 1 ..................................................................... 12 5 figure 11.21 16-bit timer/counter mode for timer 1 and block diagram ............................................. 126 figure 11.22 16-bit timer/counter mode for timer 2 ............................................................................ . 131 figure 11.23 16-bit timer/counter 2 example ................................................................................... ..... 132 figure 11.24 16-bit capture mode for timer 2 ........................................................................................ 133 figure 11.25 input capture mode operation for timer 2 ........................................................................ 134 figure 11.26 express timer overflow in capture mode ......................................................................... 1 34 figure 11.27 16-bit ppg mode for timer 2 ...................................................................................... ....... 135 figure 11.28 16-bit ppg mode timming chart for timer 2 ..................................................................... 13 6 figure 11.29 16-bit timer/counter mode for timer 2 and block diagram ............................................. 137 figure 11.30 8-bit timer/counter mode for timer 3, 4 .......................................................................... . 142 figure 11.31 16-bit timer/counter mode for timer 3 ............................................................................ . 143 figure 11.32 8-bit capture mode for timer 3, 4 ..................................................................................... 145 figure 11.33 16-bit capture mode for timer 3 ....................................................................................... 146 figure 11.34 10-bit pwm mode (force 6-ch) .................................................................................... .... 148 figure 11.35 10-bit pwm mode (force all-ch) .................................................................................. .... 149 figure 11.36 example of pwm at 4 mhz ......................................................................................... ...... 150 figure 11.37 example of changing the period in absolute duty cycle at 4 mhz .................................. 150 figure 11.38 example of pwm output waveform .................................................................................. 151 figure 11.39 example of pwm waveform in back-to-back mode at 4 mhz .......................................... 151 figure 11.40 example of phase correction and frequency correction of pwm .................................... 152 figure 11.41 example of pwm external synchronization with blnk input ........................................... 152 figure 11.42 example of force drive all channel with a-ch .................................................................. 15 3 figure 11.43 example of force drive 6-ch mode .................................................................................... 154 figure 11.44 example of pwm delay ............................................................................................. ........ 157 figure 11.45 two 8-bit timer 3, 4 block diagram ............................................................................... ... 157 figure 11.46 16-bit timer 3 block diagram ..................................................................................... ....... 158 figure 11.47 10-bit pwm timer 4 block diagram ................................................................................ . 158 figure 11.48 buzzer driver block diagram ...................................................................................... ....... 170 figure 11.49 spi 2 block diagram .............................................................................................. ............ 172 figure 11.50 spi 2 transmit/receive timing diagram at cpha = 0 ..................................................... 174 figure 11.51 spi 2 transmit/receive timing diagram at cpha = 1 ..................................................... 174
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 6 figure 11.52 12-bit adc block diagram ......................................................................................... ........ 179 figure 11.53 a/d analog input pin with capacitor .............................................................................. .... 179 figure 11.54 a/d power (avref) pin with capacitor ............................................................................ 179 figure 11.55 adc operation for align bit ................................................................................................ 180 figure 11.56 a/d converter operation flow ..................................................................................... ...... 182 figure 11.57 usi0 uart block diagram .......................................................................................... ...... 187 figure 11.58 clock generation block diagram (usi0) ........................................................................... 188 figure 11.59 synchronous mode sck0 timing (usi0) .......................................................................... 189 figure 11.60 frame format (usi0) .............................................................................................. ........... 190 figure 11.61 asynchronous start bit sampling (usi0) ........................................................................... 194 figure 11.62 asynchronous sampling of data and parity bit (usi0) ..................................................... 194 figure 11.63 stop bit sampling and next start bit sampling (usi0) ..................................................... 195 figure 11.64 usi0 spi clock formats when cpha0=0 ......................................................................... 197 figure 11.65 usi0 spi clock formats when cpha0=1 ......................................................................... 198 figure 11.66 usi0 spi block diagram ........................................................................................... ......... 199 figure 11.67 bit transfer on the i2c-bus (usi0) ............................................................................... ..... 200 figure 11.68 start and stop condition (usi0) .................................................................................. 201 figure 11.69 data transfer on the i2c-bus (usi0) .............................................................................. ... 201 figure 11.70 acknowledge on the i2c-bus (usi0) ................................................................................ . 202 figure 11.71 clock synchronization during arbitration procedure (usi0).............................................. 203 figure 11.72 arbitration procedure of two masters (usi0) .................................................................... 2 03 figure 11.73 formats and states in the master transmitter mode (usi0) ............................................. 205 figure 11.74 formats and states in the master receiver mode (usi0) ................................................. 207 figure 11.75 formats and states in the slave transmitter mode (usi0) ............................................... 209 figure 11.76 formats and states in the slave receiver mode (usi0) ................................................... 211 figure 11.77 usi0 i2c block diagram ........................................................................................... ......... 212 figure 11.78 usi1 uart block diagram .......................................................................................... ...... 224 figure 11.79 clock generation block diagram (usi1) ........................................................................... 225 figure 11.80 synchronous mode sck1 timing (usi1) .......................................................................... 226 figure 11.81 frame format (usi1) .............................................................................................. ........... 227 figure 11.82 asynchronous start bit sampling (usi1) ........................................................................... 231 figure 11.83 asynchronous sampling of data and parity bit (usi1) ..................................................... 231 figure 11.84 stop bit sampling and next start bit sampling (usi1) ..................................................... 232 figure 11.85 usi1 spi clock formats when cpha1=0 ......................................................................... 234 figure 11.86 usi1 spi clock formats when cpha1=1 ......................................................................... 235 figure 11.87 usi1 spi block diagram ........................................................................................... ......... 236 figure 11.88 bit transfer on the i2c-bus (usi1) ............................................................................... ..... 237 figure 11.89 start and stop condition (usi1) .................................................................................. 238 figure 11.90 data transfer on the i2c-bus (usi1) .............................................................................. ... 238 figure 11.91 acknowledge on the i2c-bus (usi1) ................................................................................ . 239 figure 11.92 clock synchronization during arbitration procedure (usi1).............................................. 240 figure 11.93 arbitration procedure of two masters (usi1) .................................................................... 2 40 figure 11.94 formats and states in the master transmitter mode (usi1) ............................................. 242 figure 11.95 formats and states in the master receiver mode (usi1) ................................................. 244 figure 11.96 formats and states in the slave transmitter mode (usi1) ............................................... 246 figure 11.97 formats and states in the slave receiver mode (usi1) ................................................... 248 figure 11.98 usi1 i2c block diagram ........................................................................................... ......... 249 figure 11.99 lcd circuit block diagram ................................................................................................. 261 figure 11.100 lcd signal waveforms (1/2duty, 1/2bias) ...................................................................... 26 2
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 7 figure 11.101 lcd signal waveforms (1/3duty, 1/3bias) ...................................................................... 26 3 figure 11.102 lcd signal waveforms (1/4duty, 1/3bias) ...................................................................... 26 4 figure 11.103 lcd signal waveforms (1/8duty, 1/4bias) ...................................................................... 26 5 figure 11.104 internal resistor bias connection ............................................................................... ..... 266 figure 11.105 external resistor bias connection................................................................................ ... 267 figure 11.106 lcd circuit block diagram........................................................................................ ....... 268 figure 12.1 idle mode release timing by external interrupt ............................................................... 273 figure 12.2 stop mode release timing by external interrupt .............................................................. 274 figure 12.3 stop mode release flow ............................................................................................ ....... 275 figure 13.1 reset block diagram ............................................................................................... .......... 277 figure 13.2 reset noise canceller timer diagram ............................................................................... ..... 278 figure 13.3 fast vdd rising time .............................................................................................. ............ 278 figure 13.4 internal reset release timing on power-up ................................................................... 278 figure 13.5 configuration timing when power-on ................................................................................ .. 279 figure 13.6 boot process waveform ............................................................................................. ........ 279 figure 13.7 timing diagram after reset ........................................................................................ ....... 281 figure 13.8 oscillator generating waveform example ............................................................................ . 281 figure 13.9 block diagram of bod .............................................................................................. ........... 282 figure 13.10 internal reset at the power fail situation ....................................................................... ..... 282 figure 13.11 configurati on timing when bod reset ............................................................................ 283 figure 13.12 lvi diagram ...................................................................................................... .................. 283 figure 14.1 block diagram of on-chip debug system ........................................................................... 288 figure 14.2 10-bit transmission packet ........................................................................................ .......... 288 figure 14.3 data transfer on the twin bus ..................................................................................... ....... 289 figure 14.4 bit transfer on the serial bus .................................................................................... .......... 289 figure 14.5 start and stop condition .......................................................................................... ............ 290 figure 14.6 acknowledge on the serial bus ..................................................................................... ...... 290 figure 14.7 clock synchronization during wait procedure .................................................................... 29 1 figure 14.8 connection of transmission ........................................................................................ ......... 292 figure 15.1 flash program rom structure ....................................................................................... ...... 294
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 8 list of tables table 1-1 ordering information of z51f3220 .................................................................................... ........ 12 table 5-1 normal pin description .............................................................................................. ................ 21 table 7-1 absolute maximum ratings ............................................................................................ ........... 28 table 7-2 recommended operating conditions .................................................................................... ... 28 table 7-3 a/d converter characteristics ....................................................................................... ............ 29 table 7-4 power-on reset characteristics ...................................................................................... .......... 29 table 7-5 lvr and lvi characteristics ......................................................................................... ............ 30 table 7-6 high internal rc oscillator characteristics ......................................................................... ...... 31 table 7-7 internal wdtrc oscillator characteristics ........................................................................... .... 31 table 7-8 lcd voltage characteristics ......................................................................................... ............ 32 table 7-9 dc characteristics .................................................................................................. ................... 33 table 7-10 ac characteristics ................................................................................................. .................. 35 table 7-11 spi0/1/2 characteristics ........................................................................................... ............... 36 table 7-12 uart0/1 characteristics ............................................................................................ ............. 37 table 7-13 i2c0/1 characteristics ............................................................................................. ................ 38 table 7-14 data retention voltage in stop mode ................................................................................ ..... 39 table 7-15 internal flash rom characteristics ................................................................................. ........ 40 table 7-16 input/output capacitance ........................................................................................... ............. 40 table 7-17 main clock oscillator characteristics ...................................................................................... 41 table 7-18 sub clock oscillator characteristics ............................................................................... ........ 42 table 7-19 main oscillation stabilization characteristics ..................................................................... .... 43 table 7-20 sub oscillation stabilization characteristics ...................................................................... ..... 43 table 8-1 sfr map summary ..................................................................................................... .............. 54 table 8-2 sfr map summary ..................................................................................................... .............. 55 table 8-3 sfr map ............................................................................................................. ....................... 56 table 9-1 port register map ................................................................................................... ................... 64 table 10-1 interrupt group priority level ..................................................................................... ............. 82 table 10-2 interrupt vector address table ..................................................................................... .......... 85 table 10-3 interrupt register map ............................................................................................. ................ 92 table 11-1 clock generator register map ....................................................................................... ....... 100 table 11-2 basic interval timer register map .................................................................................. ...... 103 table 11-3 watch dog timer register map ....................................................................................... ..... 106 table 11-4 watch timer register map ........................................................................................... ......... 109 table 11-5 timer 0 operating modes ...................................................................................................... 111 table 11-6 timer 0 register map ............................................................................................... ............. 118 table 11-7 timer 1 operating modes ...................................................................................................... 120 table 11-8 timer 2 register map ............................................................................................... ............. 126 table 11-9 timer 2 operating modes ...................................................................................................... 130 table 11-10 timer 3 register map .............................................................................................. ............ 137 table 11-11 timer 3, 4 operating modes......................................................................................... ....... 141 table 11-12 pwm frequency vs. resolution at 8 mhz .......................................................................... 14 7 table 11-13 pwm channel polarity .............................................................................................. .......... 147 table 11-14 timer 3, 4 register map ........................................................................................... ........... 159
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 9 table 11-15 buzzer frequency at 8 mhz ......................................................................................... ....... 170 table 11-16 buzzer driver register map ........................................................................................ ........ 171 table 11-17 spi 2 register map ................................................................................................ ............. 175 table 11-18 adc register map ............................................................................................................... 182 table 11-19 equations for calculating usi0 baud rate register setting .............................................. 188 table 11-20 cpol0 functionality................................................................................................ ............ 196 table 11-21 usi0 register map ................................................................................................. ............. 213 table 11-22 equations for calculating usi1 baud rate register setting .............................................. 225 table 11-23 cpol1 functionality................................................................................................ ............ 233 table 11-24 usi1 register map ................................................................................................. ............. 250 table 11-25 examples of usi0bd and usi1bd settings for commonly used oscillator frequencies 259 table 11-26 lcd register map .................................................................................................. ............. 268 table 12-1 peripheral operation during power down mode .................................................................. 272 table 12-2 power down operation register map ................................................................................. 276 table 13-1 reset state ........................................................................................................ .................... 277 table 13-2 boot process description ........................................................................................... ........... 280 table 13-3 reset operation register map ....................................................................................... ....... 284 table 15-1flash memory register map ........................................................................................... ....... 295
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 10 z51f3220 cmos single-chip 8-bit microcontro ller with 12-bit a/d converter 1. overview 1.1 description the z51f3220 is advanced cmos 8-bit microcontroller with 32k bytes of flash. this is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. this provides the following features : 32k bytes of flash, 256 bytes of iram, 768 bytes of xram , general purpose i/o, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit ppg output, 8-bit pwm output, 10-bit pwm output, watch timer, buzzer driving port, spi, usi, 12-bit a/d converter, lcd driver, on-chip por, lvr, lvi, on-chip oscillator and clock circuitry. the z51f3220 also supports power saving modes to reduce power consumption. device name flash xram iram adc i/o port package Z51F3220FNX 32k bytes 768 bytes 256 bytes 16 channel 42 44-pin mqfp z51f3220skx 12 channel 30 32-pin sop
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 11 1.2 features ? cpu - 8 bit cisc core (8051 compatible) ? rom (flash) capacity - 32k bytes - flash with self read/write capability - on chip debug and in-system programming (isp) - endurance : 100,000 times ? 256 bytes iram ? 768 bytes xram - (27 bytes including lcd display ram) ? general purpose i/o (gpio) - normal i/o : 9 ports (p0[2:0], p5[5:0]) - lcd shared i/o : 33 ports (p0[7:3], p1, p2, p3, p4) ? basic interval timer (bit) - 8bit 1ch - watch dog timer (wdt) - 8bit 1ch - 5khz internal rc oscillator ? timer/ counter - 8bit 1ch (t0), 16bit 2ch (t1/t2) - 8bit 2ch (t3/t4) or 16 bit 1ch (t3) ? programmable pulse generation - pulse generation (by t1/t2) - 8bit pwm (by t0) - 6-ch 10bit pwm for motor (by t4) ? watch timer (wt) - 3.91ms/0.25s/0.5s/1s/1m interval at 32.768khz ? buzzer - 8bit 1ch ? spi 2 - 8bit 1ch ? usi0/1 (uart + spi + i2c) - 8bit uart 2ch, 8bit spi 2ch and i2c 2ch ? 12 bit a/d converter - 16 input channels ? lcd driver - 21 segments and 8 common terminals - internal or external resistor bias - 1/2, 1/3, 1/4, 1/5, 1/6 and 1/8 duty selectable - resistor bias and 16-step contrast control ? power on reset - reset release level (1.4v) ? low voltage reset - 14 level detect (1.60v/ 2.00v/ 2.10v/ 2.20v/ 2.32v/ 2.44v/ 2.59v/ 2.75v/ 2.93v/ 3.14v/ 3.38v/ 3.67v/ 4.00v/ 4.40v) ? low voltage indicator - 13 level detect (2.00v/ 2.10v/ 2.20v/ 2.32v/ 2.44v/ 2.59v/ 2.75v/ 2.93v/ 3.14v/ 3.38v/ 3.67v/ 4.00v/ 4.40v) ? interrupt sources - external interrupts (exint0~7, eint8, eint10, eint11, eint12) (12) - timer(0/1/2/3/4) (5) - wdt (1) - bit (1) - wt (1) - spi 2 (1) - usi0/1 (6) - adc (1) ? internal rc oscillator - inernal rc frequency: 16mhz 0.5% (t a = 25c) ? power down mode - stop, idle mode ? operating voltage and frequency - 1.8v ~ 5.5v (@32 ~ 38khz with x-tal) - 1.8v ~ 5.5v (@0.4 ~ 4.2mhz with x-tal) - 2.7v ~ 5.5v (@0.4 ~ 10.0mhz with x-tal) - 3.0v ~ 5.5v (@0.4 ~ 12.0mhz with x-tal) - 1.8v ~ 5.5v (@0.5 ~ 8.0mhz with internal rc) - 2.0v ~ 5.5v (@0.5 ~ 16.0mhz with internal rc) - voltage dropout converter included for core ? minimum instruction execution time - 125ns (@ 16mhz main clock) - 61 s (@t 32.768khz sub clock) ? operating temperature: ? 40 ~ + 85 ? oscillator type - 0.4-12mhz crystal or ceramic for main clock - 32.768khz crystal for sub clock ? package type - 44 mqfp-1010 - 32 sop - 28 sop - pb-free package
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 12 1.3 ordering information table 1-1 ordering information of z51f3220 device name rom size iram size xram size package Z51F3220FNX 32k bytes flash 256 bytes 768 bytes 44-pin mqfp z51f3220skx 32-pin sop
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 13 1.3.1 part number suffix designation zilog part numbers consist of a number of components, as indicated in the following example. example: part number Z51F3220FNX is an 8-bit mcu with 32 kb of flash memory and 1 kb of ram in a 44-pin mqfp package and operating within a ?40c to +85c temperature range. in accordance with rohs standards, this device has been built using lead-free solder. z51 f 32 20 f n x temperature range x = ?40c to +85c pin count n = 44 pins s = 32 pins package f = mqfp j = sop device type flash memory size 32 = 32 kb flash flash memory f = general-purpose flash device family z51 = z8051 8-bit core mcu 1.4 development tools 1.4.1 compiler we do not provide the compiler. please contact the third parties. the core of z51f3220 is mentor 8051. and, device rom size is smaller than 32k bytes. developer can use all kinds of third party?s standard 8051 compiler. 1.4.2 ocd emulator and debugger the ocd (on chip debug) emulator supports zilog?s 8051 series mcu emulation. the ocd interface uses two-wire interfacing between pc and mcu which is attached to user?s system. the ocd can read or change the value of mcu internal memory and i/o peripherals. and the ocd also controls mcu internal debugging logic, it means ocd controls emulation, step run, monitoring, etc. the ocd debugger program works on microsoft-windows nt, 2000, xp, vista (32bit) operating system.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 14 if you want to see more details, please refer to ocd debugger manual. you can download debugger s/w and manual from our web-site. connection: - sclk (z51f3220 p01 port) - sdata (z51f3220 p00 port) ocd connector diagram: connect ocd with user system
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 15 1.4.3 programmer single programmer: pgmplus usb: it programs mcu device directly. ocd emulator: it can write code in mcu device too, because ocd debugging supports isp (in system programming). it does not require additional h/w, except developer?s target system. gang programmer: it programs 8 mcu devices at once. so, it is mainly used in mass production line. gang programmer is standalone type, it means it does not require host pc, after a program is downloaded from host pc to gang programmer. figure 1.1 standalone gang8 (for mass production)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 16 2. block diagram vdd vss m8051 core iram (256 bytes) 8 C bit timer 0 12 C bit a/d converter an0 -an5/p02 -p07 an6-an13 /p17 -p10 32k bytes flash t0o /pw m 0o/ p53 eint10/p54 ec0/p52 p51/xin p 52/eint8/ec0/blnk sxin/p53 /t0o /pwm0o watch timer mosi2/p14 miso2/p15 sck 2/p16 spi2 ss 2/p17 buzzer buzo/p13/seg 17/an10 /ec1 xram (768 bytes) 16 C bit timer 1 t1o /pw m 1o/ p12 eint11/p12 ec1/p13 t2o /pw m 2o/ p11 eint12/p11 16 C bit timer 2 p0 port p00/ec3/dsda p01/t3o/dscl p02/an0/avref/eint0/t4o/pwm4aa p 03/seg 26/an1/eint1/pwm4ab p04/seg 25/an2/eint2/pwm4ba p05/seg 24/an3/eint3/pwm4bb p06 /seg 23 /an4 /eint4/pwm4 ca p07 /seg 22 /an5 /eint5/pwm4 cb usi0 uart0 spi0 i2 c0 txd0/p41 rx0/p40 mosi0/p41 miso0/p40 sck 0/p42 ss 0/p43 sda 0/p41 scl 0/p40 txd1/p20 rxd1/p10 mosi1/p20 miso1/p10 sck 1/p21 ss 1/p22 sda 1/p20 scl 1/p10 watchdog timer 5khz int -rc osc basic interval timer power on reset low voltage reset lcd driver/ controller com0-com1/p37-p 36 com2-com7/seg0 -seg5/p35 -p30 seg 6-seg 29/p27-p 03 vlc 0-vlc3/p43-p40 p5 port p50/xout low voltage indicator usi1 uart1 spi1 i2 c1 on- chip debug dsda dscl int-rc osc 16mhz voltage down converter resetb /p55 sxout/p54/eint10 sxin/p53/t0 o/pwm0o xin/p51 xout/p50 clock/ system control sxout /p54/eint10 p55/resetb p1 port p 10/seg14 /an 13/rxd1 /scl 1/miso1 p 11/seg 15/an12/eint12 /t2o/pwm2o p 12/seg 16/an11/eint11 /t1o/pwm1o p13 /seg 17/an10/ec 1/buzo p 14/seg18 /an9/mosi2 p 15/seg19 /an 8/miso2 p16 /seg 20/an7/eint7 /sck2 p17/seg 21/an6/eint6/ss2 p2 port p 20/seg13 /an 14/txd1 /sda 1/mosi1 p21 /seg 12 /an15 //sck1 p22/seg 11/ss1 p23 -p27/seg 10-seg 6 p3 port p30 -p33/com7- com4 /seg 5- seg2 p34 -p35/com3- com2 /seg 1-seg 0 p36 -p37 /com1-com0 an14-an15 /p20 -p21 p41/vlc2/txd0/sda0/mosi0 p42/vlc1/sck0 p43/vlc0/ss0 p4 port p40/vlc3/rxd0/scl0/miso0 t3o/p01 ec3/p00 8 C bit timer 3 8 C bit timer 4 16 C bit timer 3 eint0/p02 t4o/p02 eint1/p03 pwm4aa/p02 pwm4ab/p03 pwm4ba/p04 pwm4bb/p05 6-ch pwm pwm4ca/p06 pwm4cb/p07 eint8/blnk/p52 avref/p02 figure 2.1 block diagram note) the p14?p17, p23?p25, p34?p37, and p43 are not in the 32-pin package.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 17 3. pin assignment =) ( 44mqfp-1010) 1 2 12 13 8 9 10 11 3 4 5 6 7 14 15 16 17 18 19 20 21 22 33 32 26 25 24 23 31 30 29 28 27 44 43 42 41 40 39 38 37 36 35 34 p55 /resetb p40/vlc3/rxd0/scl0/miso0 p41/vlc2/txd0/sda0/mosi0 p52 /eint8/e c0 /b lnk p05 /seg 24 /an3 /eint3/pwm4 bb p04 /seg 25 /an2 /eint2/pwm4 ba p54/sx out/eint1 0 p53/sxin/t0o /p wm0 o p11 /seg 15 /an12 /eint12/t2o/pwm2o p12 /seg 16 /an11 /eint11/t1o/pwm1o p17 /seg 21 /an6 /eint6/ss 2 p07 /seg 22 /an5 /eint5/pwm4 cb p15 /seg 19 /an8 /miso2 p16 /seg 20 /an7 /eint7/sck 2 p13 /seg 17 /an10 /ec1 /buzo p14 /seg 18 /an9 /mosi2 p06 /seg 23 /an4 /eint4/pwm4 ca p25 /se g8 p24 /se g9 p23 /se g10 p22 /se g11/ss 1 p21 /se g12/an15 /sck1 p20 /se g13/an14 /txd1/sda1/mosi1 p10 /se g14/an13 /rxd1/scl1/mis o1 p27 /se g6 p26 /se g7 p31 /com6/seg 4 p30 /com7/seg 5 p51 /xin p50/xout p02 /an0/av re f/eint0 /t4o /pwm4a a p0 1/t3o / dscl p00 /e c3 / dsda vdd p03/se g26/an1/eint1 /pwm4a b vs s p32 /com5/seg 3 p33 /com4/seg 2 p37/com0 p36/com1 p35 /com2/seg 0 p34 /com3/seg 1 p42 /vlc 1/sck 0 p43 /vlc0 /ss 0 figure 3.1 z51f3220 44mqfp-1010 pin assignment note) on on-chip debugging, isp uses p0[1:0] pin as dsda, dscl.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 18 =) (3 2-sop) 1 2 13 14 15 16 8 9 10 11 12 3 4 5 6 7 20 19 18 17 25 24 23 22 21 30 29 28 27 26 32 31 p22 /seg 11 /ss 1 p01 /t3o / dscl p00/ec3/ dsda p03 /seg 26 /an 1 /ei n t 1/pw m 4 ab p02 /an0 /avref /eint0/t4o /pwm4aa p51 /xin p52 /eint8/ec0/blnk p53/sxin/t0o/pwm0o p54 /sxout /eint10 vss p26/seg 7 p21 /seg 12 /an15 /sck 1 p20/seg13/an14/txd1/sda1/mosi1 vdd p50/xout p55 /resetb p40/vlc3/rxd0/scl0/miso0 p41/vlc2/txd0/sda0/mosi0 p32 /com5/seg 3 p31 /com6/seg 4 p30 /com7/seg 5 p27/seg 6 p42 /vlc 1/sck 0 p33 /com4/seg 2 p05 /seg24 /an3 /eint3/pwm4 bb p04 /seg25 /an2 /eint2/pwm4 ba p13 /seg17 /an10 /ec1/buzo p07 /seg22 /an5 /eint5/pwm4 cb p11 /seg15 /an12 /eint12/t2o/pwm2o p12 /seg16 /an11 /eint11/t1o/pwm1o p10 /seg14 /an13 /rxd1 /scl1 /miso1 p06 /seg23 /an4 /eint4/pwm4 ca figure 3.2 z51f3220 32sop pin assignment notes) 1. on on-chip debugging, isp uses p0[1:0] pin as dsda, dscl. 2. the p14-p17, p23-p25, p34-p37 and p43 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 19 4. package diagram figure 4.1 44-pin mqfp package
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 20 figure 4.2 32-pin sop package
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 21 5. pin description table 5-1 normal pin description pin name i/o function @reset shared with p00 i/o port 0 is a bit-programmable i/o port which can be configured as a schmitt-trigger input, a push-pull output, or an open-drain output. a pull-up resistor can be specified in 1-bit unit. input ec3/dsda p01 t3o/dscl p02 an0/avref/eint0/t4o/pwm4aa p03 seg26/an1/eint1/pwm4ab p04 seg25/an2/eint2/pwm4ba p05 seg24/an3/eint3/pwm4bb p06 seg23/an4/eint4/pwm4ca p07 seg22/an5/eint5/pwm4cb p10 i/o port 1 is a bit-programmable i/o port which can be configured as a schmitt-trigger input, a push-pull output, or an open-drain output. a pull-up resistor can be specified in 1-bit unit. the p14 ? p17 are not in the 32-pin package. input seg14/an13/rxd1/scl1/miso1 p11 seg15/an12/eint12/t2o/pwm2o p12 seg16/an11/eint11/t1o/pwm1o p13 seg17/an10/ec1/buzo p14 seg18/an9/mosi2 p15 seg19/an8/miso2 p16 seg20/an7/eint7/sck2 p17 seg21/an6/eint6/ss2 p20 i/o port 2 is a bit-programmable i/o port which can be configured as an input, a push-pull output, or an open-drain output. a pull-up resistor can be specified in 1-bit unit. the p23 ? p25 are not in the 32-pin package. input seg13/an14/txd1/sda1/mosi1 p21 seg12/an15/sck1 p22 seg11/ss1 p23 seg10 p24 seg9 p25 seg8 p26 seg7 p27 seg6 p30 i/o port 3 is a bit-programmable i/o port which can be configured as an input, a push-pull output. a pull-up resistor can be specified in 1-bit unit. the p34 ? p37 are only in the 44-pin package. input com7/seg5 p31 com6/seg4 p32 com5/seg3 p33 com4/seg2 p34 com3/seg1 p35 com2/seg0 p36 com1 p37 com0 p40 i/o port 4 is a bit-programmable i/o port which can be configured as an input, a push-pull output, or an open-drain output. a pull-up resistor can be specified in 1-bit unit. the p43 is only in the 44-pin package. input vlc3/rxd0/scl0/miso0 p41 vlc2/txd0/sda0/mosi0 p42 vlc1/sck0 p43 vlc0/ss0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 22 table 5-1 normal pin description (continued) pin name i/o function @reset shared with p50 i/o port 5 is a bit-programmable i/o port which can be configured as a schmitt-trigger input or a push-pull output. a pull-up resistor can be specified in 1-bit unit. input xout p51 xin p52 eint8/ec0/blnk p53 sxin/t0o/pwm0o p54 sxout/eint10 p55 resetb eint0 i/o external interrupt input and timer 3 capture input input p02/an0/avref/t4o/pwm4aa eint1 i/o external interrupt input and timer 4 capture input input p03/seg26/an1/pwm4ab eint2 i/o external interrupt inputs input p04/seg25/an2/pwm4ba eint3 p05/seg24/an3/pwm4bb eint4 p06/seg23/an4/pwm4ca eint5 p07/seg22/an5/pwm4cb eint6 p17/seg21/an6/ss2 eint7 p16/seg20/an7/sck2 eint8 p52/ec0/blnk eint10 i/o external interrupt input and timer 0 capture input input p54/sxout eint11 i/o external interrupt input and timer 1 capture input input p12/seg16/an11/t1o/pwm1o eint12 i/o external interrupt input and timer 2 capture input input p11/seg15/an12/t2o/pwm2o t0o i/o timer 0 interval output input p53/sxin/pwm0o t1o i/o timer 1 interval output input p12/seg16/an11/eint11/pwm1o t2o i/o timer 2 interval output input p11/seg15/an12/eint12/pwm2o t3o i/o timer 3 interval output input p01/dscl t4o i/o timer 4 interval output input p02/an0/avref/eint0/pwm4aa pwm0o i/o timer 0 pwm output input p53/sxin/t0o pwm1o i/o timer 1 pwm output input p12/seg16/an11/eint11/t1o pwm2o i/o timer 2 pwm output input p11/seg15/an12/eint12/t2o pwm4aa i/o timer 4 pwm outputs input p02/an0/avref/eint0/t4o pwm4ab p03/seg26/an1/eint1 pwm4ba p04/seg25/an2/eint2 pwm4bb p05/seg24/an3/eint3 pwm4ca p06/seg23/an4/eint4 pwm4cb p07/seg22/an5/eint5 blnk i/o external sync signal input for 6-ch pwms input p52/eint8/ec0 ec0 i/o timer 0 event count input input p52/eint8/blnk ec1 i/o timer 1 event count input input p13/seg17/an10 ec3 i/o timer 3 event count input input p00/dsda
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 23 table 5-1 normal pin description (continued) pin name i/o function @reset shared with buzo i/o buzzer signal outp ut input p13/seg17/an10/ec1 sck0 i/o serial 0 clock input/output input p42/vlc1 sck1 i/o serial 1 clock input/output input p21/seg12/an15 sck2 i/o serial 2 clock input/output input p16/seg20/an7/eint7 mosi0 i/o spi 0 master output, slave input input p41/vlc2/txd0/sda0 mosi1 i/o spi 1 master output, slave input input p20/seg13/an14/txd1/sda1 mosi2 i/o spi 2 master output, slave input input p14/seg18/an9 miso0 i/o spi 0 master input, slave output input p40/vlc3/rxd0/scl0 miso1 i/o spi 1 master input, slave output input p10/seg14/an13/rxd1/scl1 miso2 i/o spi 2 master input, slave output input p15/seg19/an8 ss0 i/o spi 0 slave select input input p43/vlc0 ss1 i/o spi 1 slave select input input p22/seg11 ss2 i/o spi 2 slave select input input p17/seg21/an6/eint6 txd0 i/o uart 0 data output input p41/vlc2/sda0/mosi0 txd1 i/o uart 1 data output input p20/seg13/an14/sda1/mosi1 rxd0 i/o uart 0 data input input p40/vlc3/scl0/miso0 rxd1 i/o uart 1 data input input p10/seg14/an13/scl1/miso1 scl0 i/o i2c 0 clock input/output input p40/vlc3/rxd0/miso0 scl1 i/o i2c 1 clock input/output input p10/seg14/an13/rxd1/miso1 sda0 i/o i2c 0 data input/output input p41/vlc2/txd0/mosi0 sda1 i/o i2c 1 data input/output input p20/seg13/an14/txd1/mosi1 avref i/o a/d converter reference voltage input p02/an0/eint0/t4o/pwm4aa an0 i/o a/d converter analog input channels input p02/avref/eint0/t4o/pwm4aa an1 p03/seg26/eint1/pwm4ab an2 p04/seg25/eint2/pwm4ba an3 p05/seg24/eint3/pwm4bb an4 p06/seg23/eint4/pwm4ca an5 p07/seg22/eint5/pwm4cb an6 p17/seg21/eint6/ss2 an7 p16/seg20/eint7/sck2 an8 p15/seg19/miso2 an9 p14/seg18/mosi2 an10 p13/seg17/ec1 an11 p12/seg16/eint11/t1o/pwm1o an12 p11/seg15/eint12/t2o/pwm2o an13 p10/seg14/rxd1/scl1/miso1 an14 p20/seg13/txd1/sda1/mosi1 an15 p21/seg12/sck1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 24 table 5-1 normal pin description (continued) pin name i/o function @reset shared with vlc0 i/o lcd bias voltage pins input p43/ss0 vlc1 p42/sck0 vlc2 p41/txd0/sda0/mosi0 vlc3 p40/rxd0/scl0/miso0 com0? com1 i/o lcd common signal outputs input p37?p36 com2? com3 p35?p34/seg0?seg1 com4? com7 p33?p30/seg2?seg5 seg0? seg1 i/o lcd segment signal outputs input p35?p34/com2?com3 seg2? seg5 p33?p30/com4?com7 seg6? seg10 p27?p23 seg11 p22/ss1 seg12 p21/sck1/an15 seg13 p20/an14/txd1/sda1/mosi1 seg14 p10/an13/rxd1/scl1/miso1 seg15 p11/an12/eint12/t2o/pwm2o seg16 p12/an11/eint11/t1o/pwm1o seg17 p13/an10/ec1 seg18 p14/an9/mosi2 seg19 p15/an8/miso2 seg20 p16/an7/eint7/sck2 seg21 p17/an6/eint6/ss2 seg22 p07/an5/eint5/pwm4cb seg23 p06/an4/eint4/pwm4ca seg24 p05/an3/eint3/pwm4bb seg25 p04/an2/eint2/pwm4ba seg26 p03/an1/eint1/pwm4ab
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 25 table 5-1 normal pin description (continued) pin name i/o function @reset shared with resetb i/o system reset pin with a pull-up resistor when it is selected as the resetb by configure option input p55 dsda i/o on chip debugger data input/output (note4,5) input p00/ec3 dscl i/o on chip debugger clock input (note4,5) input p01/t3o xin i/o main oscillator pins input p51 xout p50 sxin i/o sub oscillator pins input p53/t0o/pwm0o sxout p54/eint10 vdd, vss ? power input pins ? ? notes) 1. the p14?p17, p23?p25, p34?p37, and p43 are not in the 32-pin package. 2. the p55/resetb pin is configured as one of the p55 and resetb pin by the ?configure option.? 3. if the p00/ec3/dsda and p01/t3o/dscl pins are connected to an emulator during the resetor power-on reset, the pins are automatically configured as the debugger pins. 4. the p00/ec3/dsda and p01/t3o/dscl pins are configured as inputs with internal pull-up resistor only during the reset or power-on reset. 5. the p50/xout, p51/xin, p53/sxint/t0o/pwm0o, and p54/sxout/eint10 pins are configured as a function pin by software control.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 26 6. port structures 6.1 general purpose i/o port pull-up register v dd v dd pad v dd open drain register data register direction register mux 0 1 mux 1 0 cmos or schmitt level input analog channel enable analog input portx input or sub-func data input sub-func direction sub-func enable sub-func data output level shift (extvdd to 1.8v) level shift (1.8v to extvdd) figure 6.1 general purpose i/o port
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 27 6.2 external interrupt i/o port pull-up register v dd v dd pad v dd open drain register data register direction register mux 0 1 mux 1 0 interrupt enable external interrupt q d cp r vdd flag clear polarity reg. mux 1 0 debounce enable q d cp r debounce clk cmos or schmitt level input analog channel enable analog input portx input or sub-func data input sub-func direction sub-func enable sub-func data output level shift (extvdd to 1.8v) level shift (1.8v to extvdd) figure 6.2 external interrupt i/o port
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 28 7. electrical characteristics 7.1 absolute maximum ratings table 7-1 absolute maximum ratings parameter symbol rating unit note supply voltage vdd -0.3 ~ +6.5 v ? normal voltage pin v i -0.3 ~ vdd+0.3 v voltage on any pin with respect to vss v o -0.3 ~ vdd+0.3 v i oh -10 ma maximum current output sourced by (i oh per i/o pin) i oh -80 ma maximum current ( i oh ) i ol 60 ma maximum current sunk by (i ol per i/o pin) i ol 120 ma maximum current ( i ol ) total power dissipation p t 600 mw ? storage temperature t stg -65 ~ +150 c ? note) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 recommended oper ating conditions table 7-2 recommended operating conditions (t a = -40c ~ +85c) parameter symbol conditions min typ max unit operating voltage vdd f x = 32 ~ 38khz sx-tal 1.8 ? 5.5 v f x = 0.4 ~ 4.2mhz x-tal 1.8 ? 5.5 f x = 0.4 ~ 10.0mhz 2.7 ? 5.5 f x = 0.4 ~ 12.0mhz 3.0 ? 5.5 f x = 0.5 ~ 8.0mhz internal rc 1.8 ? 5.5 f x = 0.5 ~ 16.0mhz 2.0 ? 5.5 operating temperature t opr vdd= 1.8 ~ 5.5v -40 ? 85 c
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 29 7.3 a/d converter characteristics table 7-3 a/d converter characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol conditions min typ max unit resolution ? ? ?- 12 ? bit integral linear error ile avref= 2.7v ? 5.5v fx= 8mhz ? ? 3 lsb differential linearity error dle ? ? 1 zero offset error zoe ? ? 3 full scale error fse ? ? 3 conversion time t con 12bit resolution, 8mhz 20 ? ? s analog input voltage v an ? vss ? avref v analog reference voltage avref ? 1.8 ? vdd analog input leakage current i an avref= 5.12v ? ? 2 a adc operating current i adc enable vdd= 5.12v ? 1 2 ma disable ? ? 0.1 a notes) 1. zero offset error is the difference between 0000000000 and the converted output for zero input voltage (vss). 2. full scale error is the difference between 1111111111 and the converted output for full-scale input voltage (avref). 7.4 power-on reset characteristics table 7-4 power-on reset characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol condit ions min typ max unit reset release level v por ? ? 1.4 ? v vdd voltage rising time t r ? 0.05 ? ? v/ms por current i por ? ? 0.2 ? a
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 30 7.5 low voltage reset and low vo ltage indicator characteristics table 7-5 lvr and lvi characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol conditions min typ max unit detection level v lvr v lvi the lvr can select all levels but lvi can select other levels except 1.60v. ? 1.60 1.75 v 1.85 2.00 2.15 1.95 2.10 2.25 2.05 2.20 2.35 2.17 2.32 2.47 2.29 2.44 2.59 2.39 2.59 2.79 2.55 2.75 2.95 2.73 2.93 3.13 2.94 3.14 3.34 3.18 3.38 3.58 3.37 3.67 3.97 3.70 4.00 4.30 4.10 4.40 4.70 hysteresis v ? ? 10 100 mv minimum pulse width t lw ? 100 ? ? s lvr and lvi current i bl enable (both) vdd= 3v ? 10.0 15.0 a enable (one of two) ? 8.0 12.0 disable (both) ? ? 0.1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 31 7.6 high internal rc oscillator characteristics table 7-6 high internal rc oscillator characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol conditions min typ max unit frequency f irc v dd = 2.0 ? 5.5 v ? 16 ? mhz tolerance ? t a = 25c ? ? 0.5 % t a = 0c to +70c 1 t a = -20c to +80c 2 t a = -40c to +85c 3 clock duty ratio tod ? 40 50 60 % stabilization time t hfs ? ? ? 100 s irc current i irc enable ? 0.2 ? ma disable ? ? 0.1 a 7.7 internal watch-dog timer rc oscillator characteristics table 7-7 internal wdtrc oscillator characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol condit ions min typ max unit frequency f wdtrc ? 2 5 10 khz stabilization time t wdts ? ? ? 1 ms wdtrc current i wdtrc enable ? 1 ? a disable ? ? 0.1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 32 7.8 lcd voltage characteristics table 7-8 lcd voltage characteristics (t a = -40c ~ +85c, vdd= 2.0v ~ 5.5v, vss= 0v) parameter symbol conditions min typ max unit lcd voltage v lc0 lcd contrast disabled, 1/4 bias typx0.95 vdd typx1.05 v lcd contrast enabled, 1/4 bias, no panel load lcdccr=00h typx0.9 vddx16/31 typx1.1 v lcdccr=01h vddx16/30 lcdccr=02h vddx16/29 lcdccr=03h vddx16/28 lcdccr=04h vddx16/27 lcdccr=05h vddx16/26 lcdccr=06h vddx16/25 lcdccr=07h vddx16/24 lcdccr=08h vddx16/23 lcdccr=09h vddx16/22 lcdccr=0ah vddx16/21 lcdccr=0bh vddx16/20 lcdccr=0ch vddx16/19 lcdccr=0dh vddx16/18 lcdccr=0eh vddx16/17 lcdccr=0fh vddx16/16 lcd mid bias voltage(note) v lc1 vdd=2.7v to 5.5v, lcd clock = 0hz, 1/4 bias, no panel load typx0.9 3/4xvlc0 typx1.1 v v lc2 typx0.9 2/4xvlc0 typx1.1 v lc3 typx0.9 1/4xvlc0 typx1.1 lcd driver output impedance r lo vlcd=3v, iload= 10ua ? 5 10 k ? lcd bias dividing resistor r lcd t a = 25 ? c 40 60 80 note) it is middle output voltage when the vdd and the v lc0 node are connected.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 33 7.9 dc characteristics table 7-9 dc characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v, f xin = 12mhz) parameter symbol conditions min typ max unit input high voltage v ih1 p0, p1, p5, resetb 0.8vdd ? vdd v v ih2 all input pins except v ih1 0.7vdd ? vdd v input low voltage v il1 p0, p1, p5, resetb ? ? 0.2vdd v v il2 all input pins except v il1 ? ? 0.3vdd v output high voltage v oh vdd= 4.5v, i oh = -2ma, all output ports; vdd-1.0 ? ? v output low voltage v ol1 vdd=4.5v, i ol = 10ma; all output ports except v ol2 ? ? 1.0 v ol2 vdd= 4.5v, i ol = 15ma ; p1 ? ? 1.0 v input high leakage current i ih all input ports ? ? 1 a input low leakage current i il all input ports -1 ? ? a pull-up resistor r pu vi=0v, t a = 25c all input ports vdd=5.0v 25 50 100 k ? vdd=3.0v 50 100 200 vi=0v, t a = 25c resetb vdd=5.0v 150 250 400 k ? vdd=3.0v 300 500 700 osc feedback resistor r x1 xin= vdd, xout= vss t a = 25c, vdd= 5v 600 1200 2000 k ? r x2 sxin=vdd, sxout=vss t a = 25 c ,vdd=5v 2500 5000 10000
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 34 table 7-9 dc characteristics (continued) (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v, f xin = 12mhz) parameter symbol condition min typ max unit supply current i dd1 (run) f xin = 12mhz, vdd= 5v10% ? 3.0 6.0 ma f xin = 10mhz, vdd= 3v10% ? 2.2 4.4 f irc = 16mhz, vdd= 5v10% ? 3.0 6.0 i dd2 (idle) f xin = 12mhz, vdd= 5v10% ? 2.0 4.0 ma f xin = 10mhz, vdd= 3v10% ? 1.3 2.6 f irc = 16mhz, vdd= 5v10% ? 1.5 3.0 i dd3 f xin = 32.768khz vdd= 3v10% t a = 25c sub run ? 50.0 80.0 a i dd4 sub idle ? 8.0 16.0 a i dd5 stop, vdd= 5v10%, t a = 25c ? 0.5 3.0 a notes) 1. where the f xin is an external main oscillator, f sub is an external sub oscillator, the f irc is an internal rc oscillator, and the fx is the selected system clock. 2. all supply current items don?t include the current of an internal watch-dog timer rc (wdtrc) oscillator and a peripheral block. 3. all supply current items include the current of the power-on reset (por) block.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 35 7.10 ac characteristics table 7-10 ac characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) parameter symbol conditions min typ max unit resetb input low width t rsl input, vdd= 5v 10 ? ? s interrupt input high, low width t inth , t intl all interrupt, vdd= 5v 200 ? ? ns external counter input high, low pulse width t ecwh , t ecwl ecn, v dd = 5 v (n= 0, 1, 3) 200 ? ? external counter transition time t rec , t fec ecn, v dd = 5 v (n= 0, 1, 3) 20 ? ? t iwh t iwl external interrupt t rst 0.2vdd 0.2vdd 0.8vdd resetb t ecwh t ecwl ecn 0.2vdd 0.8vdd t fec t rec figure 7.1 ac timing
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 36 7.11 spi0/1/2 characteristics table 7-11 spi0/1/2 characteristics (t a = -40c ? +85c, vdd= 1.8v ? 5.5v) parameter symbol conditions min typ max unit output clock pulse period t sck internal sck source 200 ? ? ns input clock pulse period external sck source 200 ? ? output clock high, low pulse width t sckh , t sckl internal sck source 70 ? ? input clock high, low pulse width external sck source 70 ? ? first output clock delay time t fod internal/external sck source 100 ? ? output clock delay time t ds ? ? ? 50 input setup time t dis ? 100 ? ? input hold time t dih ? 150 ? ? ssn (output /input ) sckn (cpoln=0) (output /input ) sckn (cpoln=1) (output /input ) mison/mosin (data input ) t fod t sck t sckl t sckh 0.8vdd 0.2vdd msb lsb t dis t dih mison/mosin (data output ) msb lsb t ds note) n =0, 1 and 2 figure 7.2 spi0/1/2 timing
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 37 7.12 uart0/1 characteristics table 7-12 uart0/1 characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, f xin =11.1mhz) parameter symbol min typ max unit serial port clock cycle time t sck 1250 t cpu x 16 1650 ns output data setup to clock rising edge t s1 590 t cpu x 13 ? ns clock rising edge to input data valid t s2 ? ? 590 ns output data hold after clock rising edge t h1 t cpu - 50 t cpu ? ns input data hold after clock rising edge t h2 0 ? ? ns serial port clock high, low level width t high , t low 470 t cpu x 8 970 ns t high t low t sck figure 7.3 waveform for uart0/1 timing characteristics shift clock data out d1 d2 d3 d4 d5 d6 d7 d0 valid data in valid valid valid valid valid valid valid t sck t s1 t h1 t h2 t s2 figure 7.4 timing waveform for the uart0/1 module
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 38 7.13 i2c0/1 characteristics table 7-13 i2c0/1 characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) parameter symbol standard mode high-speed mode unit min max min max clock frequency t scl 0 100 0 400 khz clock high pulse width t sclh 4.0 ? 0.6 ? s clock low pulse width t scll 4.7 ? 1.3 ? bus free time t bf 4.7 ? 1.3 ? start condition setup time t stsu 4.7 ? 0.6 ? start condition hold time t sthd 4.0 ? 0.6 ? stop condition setup time t spsu 4.0 ? 0.6 ? stop condition hold time t sphd 4.0 ? 0.6 ? output valid from clock t vd 0 ? 0 ? data input hold time t dih 0 ? 0 1.0 data input setup time t dis 250 ? 100 ? ns scln sdan t stsu t sthd sdan out t sclh t scll t dih t dis t vd t vd t spsu t sphd t bf t scl note) n= 0, and 1 figure 7.5 i2c0/1 timing
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 39 7.14 data retention voltage in stop mode table 7-14 data retention voltage in stop mode (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr vddr= 1.8v, (t a = 25c), stop mode ? ? 1 a idle mode (watchdog timer active) v dd note: twait is the same as (the selected bit overflow of bit) x 1/(bit clock) int request execution of stop instruction ~ ~ data retention ~ ~ stop mode normal operating mode 0. 8v dd t wait v dddr figure 7.6 stop mode release timing when initiated by an interrupt note : twait is the same as (4096 x 4 x 1/fx) (16.4ms @ 1mhz) vdd resetb execution of stop instruction ~ ~ data retention ~ ~ stop mode oscillation stabillization time normal operating mode twait reset occurs 0. 2 vdd v dddr 0. 8 vdd figure 7.7 stop mode release timing when initiated by resetb
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 40 7.15 internal flash rom characteristics table 7-15 internal flash rom characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v, vss= 0v) parameter symbol condition min typ max unit sector write time t fsw ? ? 2.5 2.7 ms sector erase time t fse ? ? 2.5 2.7 hard-lock time t fhl ? ? 2.5 2.7 page buffer reset time t fbr ? ? ? 5 s flash programming frequency f pgm ? 0.4 ? ? mhz endurance of write/erase nf we ? ? ? 100,000 times note) during a flash operation, sclk[1:0] of sccr must be set to ?00? or ?01? (int-rc osc or main x-tal for system clock). 7.16 input/output capacitance table 7-16 input/output capacitance (t a = -40c ~ +85c, vdd= 0v) parameter symbol condition min typ max unit input capacitance c in fx= 1mhz unmeasured pins are connected to vss ? ? 10 pf output capacitance c out i/o capacitance c io
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 41 7.17 main clock oscillator characteristics table 7-17 main clock oscillator characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) oscillator parameter condition min typ max unit crystal main oscillation frequency 1.8v ? 5.5v 0.4 ? 4.2 mhz 2.7v ? 5.5v 0.4 ? 10.0 3.0v ? 5.5v 0.4 ? 12.0 ceramic oscillator main oscillation frequency 1.8v ? 5.5v 0.4 ? 4.2 mhz 2.7v ? 5.5v 0.4 ? 10.0 3.0v ? 5.5v 0.4 ? 12.0 external clock xin input frequency 1.8v ? 5.5v 0.4 ? 4.2 mhz 2.7v ? 5.5v 0.4 ? 10.0 3.0v ? 5.5v 0.4 ? 12.0 xin xout c1 c2 figure 7.8 crystal/ceramic oscillator xin xout external clock source open figure 7.9 external clock
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 42 7.18 sub clock oscillator characteristics table 7-18 sub clock oscillator characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) oscillator parameter condition min typ max unit crystal sub oscillation frequency 1.8v ? 5.5v 32 32.768 38 khz external clock sxin input frequency 32 ? 100 khz sxin sxout c1 c2 figure 7.10 crystal oscillator sxin sxout external clock source open figure 7.11 external clock
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 43 7.19 main oscillation stabilization characteristics table 7-19 main oscillation stabilization characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) oscillator parameter min typ max unit crystal fx > 1mhz oscillation stabilization occurs when vdd is equal to the minimum oscillator voltage range. ? ? 60 ms ceramic ? ? 10 ms external clock f xin = 0.4 to 12mhz xin input high and low width (t xh , t xl ) 42 ? 1250 ns t xh t xl xin 0.2vdd 0.8vdd 1/f xin figure 7.12 clock timing measurement at xin 7.20 sub oscillation characteristics table 7-20 sub oscillation stabilization characteristics (t a = -40c ~ +85c, vdd= 1.8v ~ 5.5v) oscillator parameter min typ max unit crystal ? ? ? 10 s external clock sxin input high and low width (t xh , t xl ) 5 ? 15 s figure 7.13 clock timing measurement at sxin
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 44 7.21 operating voltage range 1.8 0.4mhz 3.0 5.5 12.0mhz (f xin =0.4 to 12mhz) supply voltage (v) 4. 2mhz 1.8 5.5 32.768khz supply voltage (v) (f sub =32 to 38khz) 10.0mhz 2. 7 figure 7.14 operating voltage range
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 45 7.22 recommended circuit and layout { } =) xout xin i/o vss vdd high-current part infrared led , fnd(7-segment ), ,,,,, etc { } 0.01uf vcc 0. 1 u f this 0.1uf capacitor should be within 1cm from the vdd pin of mcu on the pcb layout. { } this 0.01uf capacitor is alternatively for noise immunity. x-tal sxout sxin 32.768khz the main and sub crystal should be as close by the mcu as possible. + 0. 1 u f vdd vcc { } the mcu power line (vdd a n d vss) should be separated from the high - current part at a dc power node on the pcb layout. dc power the load capacitors of the sub clock -c1, c2: c l x 2 15% -c l = (c1 x c2)/(c1 + c2) - cstray -c l : the specific capacitor value of crystal - cstray: the parasitic capacitor of a pcb (1pf C 1.5pf) c1 c2 figure 7.15 recommended circuit and layout
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 46 7.23 typical characteristics these graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. in graphs or tables some data are out of specified operating range (e.g. out of specified vdd range). this is only for information and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ?typical? represents the mean of the distribution while ?max? or ?min? represents (mean + 3 ) and (mean - 3 ) respectively where is standard deviation. figure 7.16 run (idd1 ) current figure 7.17 idle (idd2) current 0.00 0.50 1.00 1.50 2.00 2.50 3.00 2.7v 3.0v 3.3v ma 10mhz -40 10mhz +25 10mhz +85 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 2.7v 3.0v 3.3v ma 10mhz -40 10mhz +25 10mhz +85
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 47 figure 7.18 sub run (idd3) current figure 7.19 sub idle (idd4) current 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 2.7v 3.0v 3.3v 4.5v 5.0v 5.5v ua -40 +25 +85 0.00 5.00 10.00 15.00 20.00 25.00 30.00 2.7v 3.0v 3.3v 4.5v 5.0v 5.5v ua -40 +25 +85
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 48 figure 7.20 stop (idd5) current 0.00 1.00 2.00 3.00 4.00 5.00 2.7v 3.0v 3.3v 4.5v 5.0v 5.5v ua -40 +25 +85
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 49 8. memory the z51f3220 addresses two separate address memory stores: program memory and data memory. the logical separation of program and data memory allows data memory to be accessed by 8-bit addresses, which makes the 8-bit cpu access the data memory more rapidly. nevertheless, 16-bit data memory addresses can also be generated through the dptr register. z51f3220 provides on-chip 32k bytes of the isp type flash program memory, which can be read and written to. internal data memory (iram) is 256 bytes and it includes the stack area. external data memory (xram) is 768 bytes and it includes 27 bytes of lcd display ram. 8.1 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has just 32k bytes program memory space. figure 8-1 shows the map of the lower part of the program memory. after reset, the cpu begins execution from location 0000h. each interrupt is assigned a fixed location in program memory. the interrupt causes the cpu to jump to that location, where it commences execution of the service routine. external interrupt 11, for example, is assigned to location 000bh. if external interrupt 11 is going to be used, its service routine must begin at location 000bh. if the interrupt is not going to be used, its service location is available as general purpose program memory. if an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 byte interval. longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 50 ffffh 0000h 32k bytes 7fffh - 32k bytes including interrupt vector region figure 8.1 program memory
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 51 8.2 data memory figure 8-2 shows the internal data memory space available. ffh 80h upper 128 bytes internal ram (indirect addressing ) lower 128 bytes internal ram (direct or indirect addressing ) 7fh 00h ffh 80h special function registers 128 bytes (direct addressing) figure 8.2 data memory map the internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and sfr space. internal data memory addresses are always one byte wide, which implies an address space of only 256 bytes. however, in fact the addressing modes for internal ram can accommodate up to 384 bytes by using a simple trick. direct addresses higher than 7fh access one memory space and indirect addresses higher than 7fh access a different memory space. thus figure 8-2 shows the upper 128 bytes and sfr space occupying the same block of addresses, 80h through ffh, although they are physically separate entities. the lower 128 bytes of ram are present in all 8051 devices as mapped in figure 8-3. the lowest 32 bytes are grouped into 4 banks of 8 registers. program instructions call out these registers as r0 through r7. two bits in the program status word select which register bank is in use. this allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. the next 16 bytes above the register banks form a block of bit-addressable memory space. the 8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h through 7fh. all of the bytes in the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes ram can only be accessed by indirect addressing. these spaces are used for data ram and stack.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 52 bit addressable 7fh general purpose register 30h 80 bytes 2fh 20h 16 bytes (128 bits) register bank 3 (8 bytes) 1fh 18h 8 bytes register bank 2 (8 bytes) 17h 10h 8 bytes register bank 1 (8 bytes) 0fh 08h 8 bytes register bank 0 (8 bytes) 07h 00h 8 bytes r7 r6 r5 r4 r3 r2 r1 r0 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 figure 8.3 lower 128 bytes ram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 53 8.3 xram memory z51f3220 has 768 bytes xram. this area has no relation with ram/flash. it can be read and written to through sfr with 8-bit unit. external ram 768 bytes (indirect addressing ) lcd display ram 0000 h 001ah 001bh 02ffh 107 fh 1000 h extended special function registers 128 bytes (indirect addressing ) not used figure 8.4 xdata memory area
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 54 8.4 sfr map 8.4.1 sfr map summary table 8-1 sfr map summary 00h/8h (1) 01h/9h 02h/0ah 03h/0bh 04h/0ch 05h/0dh 06h/0eh 07h/0fh 0f8h ip1 ? fsadrh fsadrm fsadrl fidr fmcr p5fsr 0f0h b usi1st1 usi1st2 usi1bd usi1sdhr usi1dr usi1sclr usi1schr 0e8h rstfr usi1cr1 usi1cr2 usi1cr3 usi1cr4 usi1sar p3fsr p4fsr 0e0h acc usi0st1 usi0st2 usi0bd usi0sdhr usi0dr usi0sclr usi0schr 0d8h lvrcr usi0cr1 usi0cr2 usi0cr3 usi0cr4 usi0sar p0db p15db 0d0h psw p5io p0fsrl p0fsrh p1fsrl p1fsrh p2fsrl p2fsrh 0c8h osccr p4io ? ? ? ? ? ? 0c0h eiflag0 p3io t2crl t2c rh t2adrl t2adrh t2bdrl t2bdrh 0b8h ip p2io t1crl t1crh t1a drl t1adrh t1bdrl t1bdrh 0b0h p5 p1io t0cr t0cnt t0dr/ t0cdr spicr spidr spisr 0a8h ie ie1 ie2 ie3 p0pu p1pu p2pu p3pu 0a0h p4 p0io eo p4pu eipol0l eipol0h eiflag1 eipol1 98h p3 lcdcrl lcdcrh lcdccr adccrh adccrh adcdrl adcdrh 90h p2 p0od p1od p2od p4od p5pu wtcr buzcr 88h p1 wtdr/ wtcnt sccr bitcr bitcnt wdtcr wdtdr/ wdtcnt buzdr 80h p0 sp dpl dph dpl1 dph1 lvicr pcon note) these registers are bit-addressable. - reserved m8051 compatible
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 55 table 8-2 sfr map summary 00h/8h (1) 01h/9h 02h/0ah 03h/0bh 04h/0ch 05h/0dh 06h/0eh 07h/0fh 1078h ? ? ? ? ? ? ? ? 1070h ? ? ? ? ? ? ? ? 1068h ? ? ? ? ? ? ? ? 1060h ? ? ? ? ? ? ? ? 1058h ? ? ? ? ? ? ? ? 1050h ? ? ? ? ? ? ? ? 1048h ? ? ? ? ? ? ? ? 1040h ? ? ? ? ? ? ? ? 1038h ? ? ? ? ? ? ? ? 1030h ? ? ? ? ? ? ? ? 1028h ? ? ? ? ? ? ? ? 1020h ? ? ? ? ? ? ? ? 1018h ? ? ? ? ? ? ? ? 1010h t4dlya t4dlyb t4dlyc t4dr t4capr t4cnt ? ? 1008h t4pprl t4pprh t4adrl t4adrh t4bdrl t4bdrh t4cdrl t4cdrh 100h t3cr t3cnt/ t3dr/ t3capr t4cr t4pcr1 t4pcr2 t4 pcr3 t4isr t4imsk note) these registers are bit-addressable. - reserved
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 56 8.4.2 sfr map table 8-3 sfr map address function symbol r/w @reset 7 6 5 4 3 2 1 0 80h p0 data register p0 r/w 0 0 0 0 0 0 0 0 81h stack pointer sp r/w 0 0 0 0 0 1 1 1 82h data pointer register low dpl r/w 0 0 0 0 0 0 0 0 83h data pointer register high dph r/w 0 0 0 0 0 0 0 0 84h data pointer register low 1 dpl1 r/w 0 0 0 0 0 0 0 0 85h data pointer register high 1 dph1 r/w 0 0 0 0 0 0 0 0 86h low voltage indicator control register lvicr r/w ? ? 0 0 0 0 0 0 87h power control register pcon r/w 0 ? ? ? 0 0 0 0 88h p1 data register p1 r/w 0 0 0 0 0 0 0 0 89h watch timer data register wtdr w 0 1 1 1 1 1 1 1 watch timer counter register wtcnt r ? 0 0 0 0 0 0 0 8ah system and clock control register sccr r/w ? ? ? ? ? ? 0 0 8bh basic interval timer control register bitcr r/w 0 0 0 ? 0 0 0 1 8ch basic interval timer counter register bitcnt r 0 0 0 0 0 0 0 0 8dh watch dog timer control register wdtcr r/w 0 0 0 ? ? ? 0 0 8eh watch dog timer data register wdtdr w 1 1 1 1 1 1 1 1 watch dog timer counter register wdtcnt r 0 0 0 0 0 0 0 0 8fh buzzer data register buzdr r/w 1 1 1 1 1 1 1 1 90h p2 data register p2 r/w 0 0 0 0 0 0 0 0 91h p0 open-drain selection register p0od r/w 0 0 0 0 0 0 0 0 92h p1 open-drain selection register p1od r/w 0 0 0 0 0 0 0 0 93h p2 open-drain selection register p2od r/w 0 0 0 0 0 0 0 0 94h p4 open-drain selection register p4od r/w ? ? ? ? 0 0 0 0 95h p5 pull-up resistor selection register p5pu r/w ? ? 0 0 0 0 0 0 96h watch timer control register wtcr r/w 0 ? ? 0 0 0 0 0 97h buzzer control register buzcr r/w ? ? ? ? ? 0 0 0 98h p3 data register p3 r/w 0 0 0 0 0 0 0 0 99h lcd driver control low register lcdcrl r/w ? ? 0 0 0 0 0 0 9ah lcd driver control high register lcdcrh r/w ? ? ? 0 ? ? 0 0 9bh lcd contrast control register lcdccr r/w 0 ? ? ? 0 0 0 0 9ch a/d converter control low register adccrl r/w 0 0 0 0 0 0 0 0 9dh a/d converter control high register adccrh r/w 0 ? 0 0 0 0 0 0 9eh a/d converter data low register adcdrl r x x x x x x x x 9fh a/d converter data high register adcdrh r x x x x x x x x
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 57 table 8-2 sfr map (continued) address function symbol r/w @reset 7 6 5 4 3 2 1 0 a0h p4 data register p4 r/w ? ? ? ? 0 0 0 0 a1h p0 direction register p0io r/w 0 0 0 0 0 0 0 0 a2h extended operation register eo r/w ? ? ? 0 ? 0 0 0 a3h p4 pull-up resistor selection register p4pu r/w ? ? ? ? 0 0 0 0 a4h external interrupt polarity 0 low register eipol0l r/w 0 0 0 0 0 0 0 0 a5h external interrupt polarity 0 high register eipol0h r/w 0 0 0 0 0 0 0 0 a6h external interrupt flag 1 register eiflag1 r/w 0 0 0 0 0 0 0 0 a7h external interrupt polarity 1 register eipol1 r/w 0 0 0 0 0 0 0 0 a8h interrupt enable register ie r/w 0 ? 0 0 0 0 0 0 a9h interrupt enable register 1 ie1 r/w ? ? 0 0 0 0 ? 0 aah interrupt enable register 2 ie2 r/w ? ? 0 0 0 0 0 0 abh interrupt enable register 3 ie3 r/w ? ? 0 0 0 0 0 0 ach p0 pull-up resistor selection register p0pu r/w 0 0 0 0 0 0 0 0 adh p1 pull-up resistor selection register p1pu r/w 0 0 0 0 0 0 0 0 aeh p2 pull-up resistor selection register p2pu r/w 0 0 0 0 0 0 0 0 afh p3 pull-up resistor selection register p3pu r/w 0 0 0 0 0 0 0 0 b0h p5 data register p5 r/w ? ? 0 0 0 0 0 0 b1h p1 direction register p1io r/w 0 0 0 0 0 0 0 0 b2h timer 0 control register t0cr r/w 0 ? 0 0 0 0 0 0 b3h timer 0 counter register t0cnt r 0 0 0 0 0 0 0 0 b4h timer 0 data register t0dr r/w 1 1 1 1 1 1 1 1 timer 0 capture data register t0cdr r 0 0 0 0 0 0 0 0 b5h spi 2 control register spicr r/w 0 0 0 0 0 0 0 0 b6h spi 2 data register spidr r/w 0 0 0 0 0 0 0 0 b7h spi 2 status register spisr r/w 0 0 0 ? 0 0 ? ? b8h interrupt priority register ip r/w ? ? 0 0 0 0 0 0 b9h p2 direction register p2io r/w 0 0 0 0 0 0 0 0 bah timer 1 control low register t1crl r/w 0 0 0 0 ? 0 0 0 bbh timer 1 counter high register t1crh r/w 0 ? 0 0 ? ? ? 0 bch timer 1 a data low register t1adrl r/w 1 1 1 1 1 1 1 1 bdh timer 1 a data high register t1adrh r/w 1 1 1 1 1 1 1 1 beh timer 1 b data low register t1bdrl r/w 1 1 1 1 1 1 1 1 bfh timer 1 bdata high register t1bdrh r/w 1 1 1 1 1 1 1 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 58 table 8-2 sfr map (continued) address function symbol r/w @reset 7 6 5 4 3 2 1 0 c0h external interrupt flag 0 register eiflag0 r/w 0 0 0 0 0 0 0 0 c1h p3 direction register p3io r/w 0 0 0 0 0 0 0 0 c2h timer 2 control low register t2crl r/w 0 0 0 0 ? 0 ? 0 c3h timer 2 control high register t2crh r/w 0 ? 0 0 ? ? ? 0 c4h timer 2 a data low register t2adrl r/w 1 1 1 1 1 1 1 1 c5h timer 2 a data high register t2adrh r/w 1 1 1 1 1 1 1 1 c6h timer 2 b data low register t2bdrl r/w 1 1 1 1 1 1 1 1 c7h timer 2 bdata high register t2bdrh r/w 1 1 1 1 1 1 1 1 c8h oscillator control register osccr r/w ? ? 0 0 1 0 0 0 c9h p4 direction register p4io r/w ? ? ? ? 0 0 0 0 cah reserved ? ? ? cbh reserved ? ? ? cch reserved ? ? ? cdh reserved ? ? ? ceh reserved ? ? ? cfh reserved ? ? ? d0h program status word register psw r/w 0 0 0 0 0 0 0 0 d1h p5 direction register p5io r/w ? ? 0 0 0 0 0 0 d2h p0 function selection low register p0fsrl r/w ? 0 0 0 0 0 0 0 d3h p0 function selection high register p0fsrh r/w ? ? 0 0 0 0 0 0 d4h p1 function selection low register p1fsrl r/w 0 0 0 0 0 0 0 0 d5h p1 function selection high register p1fsrh r/w 0 0 0 0 0 0 0 0 d6h p2 function selection low register p2fsrl r/w ? ? 0 0 0 0 0 0 d7h p2 function selection high register p2fsrh r/w ? ? ? ? 0 0 0 0 d8h low voltage reset control register lvrcr r/w 0 ? ? 0 0 0 0 0 d9h usi0 control register 1 usi0cr1 r/w 0 0 0 0 0 0 0 0 dah usi0 control register 2 usi0cr2 r/w 0 0 0 0 0 0 0 0 dbh usi0 control register 3 usi0cr3 r/w 0 0 0 0 0 0 0 0 dch usi0 control register 4 usi0cr4 r/w 0 ? ? 0 0 ? 0 0 ddh usi0 slave address register usi0sar r/w 0 0 0 0 0 0 0 0 deh p0 debounce enable register p0db r/w 0 0 0 0 0 0 0 0 dfh p1/p5 debounce enable register p15db r/w ? ? 0 0 0 0 0 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 59 table 8-2 sfr map (continued) address function symbol r/w @reset 7 6 5 4 3 2 1 0 e0h accumulator register acc r/w 0 0 0 0 0 0 0 0 e1h usi0 status register 1 usi0st1 r/w 0 0 0 0 ? 0 0 0 e2h usi0 status register 2 usi0st2 r 0 0 0 0 0 0 0 0 e3h usi0 baud rate generation register usi0bd r/w 1 1 1 1 1 1 1 1 e4h usi0 sda hold time register usi0shdr r/w 0 0 0 0 0 0 0 1 e5h usi0 data register usi0dr r/w 0 0 0 0 0 0 0 0 e6h usi0 scl low period register usi0sclr r/w 0 0 1 1 1 1 1 1 e7h usi0 scl high period register usi0schr r/w 0 0 1 1 1 1 1 1 e8h reset flag register rstfr r/w 1 x 0 0 x ? ? ? e9h usi1 control register 1 usi1cr1 r/w 0 0 0 0 0 0 0 0 eah usi1 control register 2 usi1cr2 r/w 0 0 0 0 0 0 0 0 ebh usi1 control register 3 usi1cr3 r/w 0 0 0 0 0 0 0 0 ech usi1 control register 4 usi1cr4 r/w 0 ? ? 0 0 ? 0 0 edh usi1 slave address register usi1sar r/w 0 0 0 0 0 0 0 0 eeh p3 function selection register p3fsr r/w 0 0 0 0 0 0 0 0 efh p4 function selection register p4fsr r/w ? 0 0 0 0 0 0 0 f0h b register b r/w 0 0 0 0 0 0 0 0 f1h usi1 status register 1 usi1st1 r/w 0 0 0 0 ? 0 0 0 f2h usi1 status register 2 usi1st2 r 0 0 0 0 0 0 0 0 f3h usi1 baud rate generation register usi1bd r/w 1 1 1 1 1 1 1 1 f4h usi1 sda hold time register usi1shdr r/w 0 0 0 0 0 0 0 1 f5h usi1 data register usi1dr r/w 0 0 0 0 0 0 0 0 f6h usi1 scl low period register usi1sclr r/w 0 0 1 1 1 1 1 1 f7h usi1 scl high period register usi1schr r/w 0 0 1 1 1 1 1 1 f8h interrupt priority register 1 ip1 r/w ? ? 0 0 0 0 0 0 f9h reserved ? ? ? fah flash sector address high register fsadrh r/w ? ? ? ? 0 0 0 0 fbh flash sector address middle register fsadrm r/w 0 0 0 0 0 0 0 0 fch flash sector address low register fsadrl r/w 0 0 0 0 0 0 0 0 fdh flash identification register fidr r/w 0 0 0 0 0 0 0 0 feh flash mode control register fmcr r/w 0 ? ? ? ? 0 0 0 ffh p5 function selection register p5fsr r/w ? ? 0 0 0 0 0 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 60 table 8-2 sfr map (continued) address function symbol r/w @reset 7 6 5 4 3 2 1 0 1000h timer 3 control register t3cr r/w 0 ? 0 0 0 0 0 0 1001h timer 3 counter register t3cnt r 0 0 0 0 0 0 0 0 timer 3 data register t3dr w 1 1 1 1 1 1 1 1 timer 3 capture data register t3capr r 0 0 0 0 0 0 0 0 1002h timer 4 control register t4cr r/w 0 0 0 0 0 0 0 0 1003h timer 4 pwm control register 1 t4pcr1 r/w 0 0 0 0 0 0 0 0 1004h timer 4 pwm control register 2 t4pcr2 r/w 0 0 0 0 0 0 0 0 1005h timer 4 pwm control register 3 t4pcr3 r/w ? 0 0 0 ? ? ? ? 1006h timer 4 interrupt status register t4isr r/w 0 0 0 0 0 ? ? ? 1007h timer 4 interrupt mask register t4msk r/w 0 0 0 0 0 ? ? ? 1008h timer 4 pwm period low register t4pprl r/w 1 1 1 1 1 1 1 1 1009h timer 4 pwm period high register t4pprh r/w ? ? ? ? ? ? 0 0 100ah timer 4 pwm a duty low register t4adrl r/w 0 1 1 1 1 1 1 1 100bh timer 4 pwm a duty high register t4adrh r/w ? ? ? ? ? ? 0 0 100ch timer 4 pwm b duty low register t4bdrl r/w 0 1 1 1 1 1 1 1 100dh timer 4 pwm b duty high register t4bdrh r/w ? ? ? ? ? ? 0 0 100eh timer 4 pwm c duty low register t4cdrl r/w 0 1 1 1 1 1 1 1 100fh timer 4 pwm c duty high register t4cdrh r/w ? ? ? ? ? ? 0 0 1010h timer 4 pwm a delay register t4dlya r/w 0 0 0 0 0 0 0 0 1011h timer 4 pwm b delay register t4dlyb r/w 0 0 0 0 0 0 0 0 1012h timer 4 pwm c delay register t4dlyc r/w 0 0 0 0 0 0 0 0 1013h timer 4 data register t4dr r/w 1 1 1 1 1 1 1 1 1014h timer 4 capture data register t4capr r 0 0 0 0 0 0 0 0 1015h timer 4 counter register t4cnt r 0 0 0 0 0 0 0 0 ?????????????.. 107fh reserved ? ? ?
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 61 8.4.3 compiler compatible sfr acc (accumulator register) : e0h 7 6 5 4 3 2 1 0 acc r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h acc accumulator b (b register) : f0h 7 6 5 4 3 2 1 0 b r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h b b register sp (stack pointer) : 81h 7 6 5 4 3 2 1 0 sp r/w r/w r/w r/w r/w r/w r/w r/w initial value : 07h sp stack pointer dpl (data pointer register low) : 82h 7 6 5 4 3 2 1 0 dpl r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h dpl data pointer low dph (data pointer register high) : 83h 7 6 5 4 3 2 1 0 dph r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h dph data pointer high
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 62 dpl1 (data pointer register low 1) : 84h 7 6 5 4 3 2 1 0 dpl1 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h dpl1 data pointer low 1 dph1 (data pointer register high 1) : 85h 7 6 5 4 3 2 1 0 dph1 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h dph1 data pointer high 1 psw (program status word register) : d0h 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h cy carry flag ac auxiliary carry flag f0 general purpose user-definable flag rs1 register bank select bit 1 rs0 register bank select bit 0 ov overflow flag f1 user-definable flag p parity flag. set/cleared by hardware each instruction cycle to indicate an odd/even number of ?1? bits in the accumulator eo (extended operation register) : a2h 7 6 5 4 3 2 1 0 ? ? ? trap_en ? dpsel2 dpsel1 dpsel0 ? ? ? r/w ? r/w r/w r/w initial value : 00h trap_en select the instruction (keep always ?0?) . 0 select software trap instruction 1 select movc @(dptr++), a dpsel[2:0] select banked data pointer register dpsel2 dpsel1 spsel 0 description 0 0 0 dptr0 0 0 1 dptr1 reserved
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 63 9. i/o ports 9.1 i/o ports the z51f3220 has ten groups of i/o ports (p0 ~ p5). each port can be easily configured by software as i/o pin, internal pull up and open-drain pin to meet various system configurations and design requirements. also p0 includes function that can generate interrupt according to change of state of the pin. 9.2 port register 9.2.1 data register (px) data register is a bidirectional i/o port. if ports are configured as output ports, data can be written to the corresponding bit of the px. if ports are configured as input ports, the data can be read from the corresponding bit of the px. 9.2.2 direction register (pxio) each i/o pin can be independently used as an input or an output through the pxio register. bits cleared in this register will make the corresponding pin of px to input mode. set bits of this register will make the pin to output mode. almost bits are cleared by a system reset, but some bits are set by a system reset. 9.2.3 pull-up resistor selection register (pxpu) the on-chip pull-up resistor can be connected to i/o ports individually with a pull-up resistor selection register (pxpu). the pull-up register selection controls the pull-up resister enable/disable of each port. when the corresponding bit is 1, the pull-up resister of the pin is enabled. when 0, the pull-up resister is disabled. all bits are cleared by a system reset. 9.2.4 open-drain selection register (pxod) there are internally open-drain selection registers (pxod) for p0 ~ p4 and a bit for p5. the open-drain selection register controls the open-drain enable/disable of each port. almost ports become push-pull by a system reset, but some ports become open-drain by a system reset. 9.2.5 debounce enable register (pxdb) p0[7:2], p1[2:1], p1[7:6], p52 and p54 support debounce function. debounce clocks of each ports are fx/1, fx/4, and fx/4096. 9.2.6 port function selection register (pxfsr) these registers define alternative functions of ports. please remember that these registers should be set properly for alternative port function. a reset clears the pxfsr register to ?00h?, which makes all pins to normal i/o ports.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 64 9.2.7 register map table 9-1 port register map name address dir default description p0 80h r/w 00h p0 data register p0io a1h r/w 00h p0 direction register p0pu ach r/w 00h p0 pull-up resistor selection register p0od 91h r/w 00h p0 open-drain selection register p0db deh r/w 00h p0 debounce enable register p0fsrh d3h r/w 00h p0 function selection high register p0fsrl d2h r/w 00h p0 function selection low register p1 88h r/w 00h p1 data register p1io b1h r/w 00h p1 direction register p1pu adh r/w 00h p1 pull-up resistor selection register p1od 92h r/w 00h p1 open-drain selection register p15db dfh r/w 00h p1/p5 debounce enable register p1fsrh d5h r/w 00h p1 function selection high register p1fsrl d4h r/w 00h p1 function selection low register p2 90h r/w 00h p2 data register p2io b9h r/w 00h p2 direction register p2pu aeh r/w 00h p2 pull-up resistor selection register p2od 93h r/w 00h p2 open-drain selection register p2fsrh d7h r/w 00h p2 function selection high register p2fsrl d6h r/w 00h p2 function selection low register p3 98h r/w 00h p3 data register p3io c1h r/w 00h p3 direction register p3pu afh r/w 00h p3 pull-up resistor selection register p3fsr eeh r/w 00h p3 function selection register p4 a0h r/w 00h p4 data register p4io c9h r/w 00h p4 direction register p4pu a3h r/w 00h p4 pull-up resistor selection register p4od 94h r/w 00h p4 open-drain selection register p4fsr efh r/w 00h p4 function selection register p5 b0h r/w 00h p5 data register p5io d1h r/w 00h p5 direction register p5pu 95h r/w 00h p5 pull-up resistor selection register p5fsr efh r/w 00h p5 function selection register
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 65 9.3 p0 port 9.3.1 p0 port description p0 is 8-bit i/o port. p0 control registers consist of p0 data register (p0), p0 direction register (p0io), debounce enable register (p0db), p0 pull-up resistor selection register (p0pu), and p0 open-drain selection register (p0od). refer to the port function selection registers for the p0 function selection. 9.3.2 register description for p0 p0 (p0 data register) : 80h 7 6 5 4 3 2 1 0 p07 p06 p05 p04 p03 p02 p01 p00 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p0[7:0] i/o data p0io (p0 direction register) : a1h 7 6 5 4 3 2 1 0 p07io p06io p05io p04io p03io p02io p01io p00io r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p0io[7:0] p0 data i/o direction. 0 input 1 output note: ec3/eint0 ~ eint5 function possible when input p0pu (p0 pull-up resistor selection register) : ach 7 6 5 4 3 2 1 0 p07pu p06pu p05pu p04pu p03pu p02pu p01pu p00pu r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p0pu[7:0] configure pull-up resistor of p0 port 0 disable 1 enable p0od (p0 open-drain selection register) : 91h 7 6 5 4 3 2 1 0 p07od p06od p05od p04od p03od p02od p01od p00od r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p0od[7:0] configure open-drain of p0 port 0 push-pull output 1 open-drain output
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 66 p0db (p0 debounce enable register) : deh 7 6 5 4 3 2 1 0 dbclk1 dbclk0 p07db p06db p05db p04db p03db p02db r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h dbclk[1:0] configure debounce clock of port dbclk1 dbclk0 description 0 0 fx/1 0 1 fx/4 1 0 fx/4096 1 1 reserved p07db configure debounce of p07 port 0 disable 1 enable p06db configure debounce of p06 port 0 disable 1 enable p05db configure debounce of p05 port 0 disable 1 enable p04db configure debounce of p04 port 0 disable 1 enable p03db configure debounce of p03port 0 disable 1 enable p02db configure debounce of p02 port 0 disable 1 enable notes) 1. if the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. a pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. the port debounce is automatically disabled at stop mode and recovered after stop mode release.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 67 9.4 p1 port 9.4.1 p1 port description p1 is 8-bit i/o port. p1 control registers consist of p1 data register (p1), p1 direction register (p1io), debounce enable register (p15db), p1 pull-up resistor selection register (p1pu), and p1 open-drain selection register (p1od) . refer to the port function selection registers for the p1 function selection. 9.4.2 register description for p1 p1 (p1 data register) : 88h 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p1[7:0] i/o data p1io (p1 direction register) : b1h 7 6 5 4 3 2 1 0 p17io p16io p15io p14io p13io p12io p11io p10io r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p1io[7:0] p1 data i/o direction 0 input 1 output note: eint6/enint7/eint11/eint12/ss2/ec1 function possibl when input p1pu (p1 pull-up resistor selection register) : adh 7 6 5 4 3 2 1 0 p17pu p16pu p15pu p14pu p13pu p12pu p11pu p10pu r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p1pu[7:0] configure pull-up resistor of p1 port 0 disable 1 enable p1od (p1 open-drain selection register) : 92h 7 6 5 4 3 2 1 0 p17od p16od p15od p14od p13od p12od p11od p10od r/w r/w r/w r/w r/w r/w r/w r/w initial value : 08h p1od[7:0] configure open-drain of p1 port 0 push-pull output 1 open-drain output
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 68 p15db (p1/p5 debounce enable register) : dfh 7 6 5 4 3 2 1 0 ? ? p54db p52db p17db p16db p12db p11db ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p54db configure debounce of p54 port 0 disable 1 enable p52db configure debounce of p52 port 0 disable 1 enable p17db configure debounce of p17 port 0 disable 1 enable p16db configure debounce of p16 port 0 disable 1 enable p12db configure debounce of p12 port 0 disable 1 enable p11db configure debounce of p11 port 0 disable 1 enable notes) 1. if the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. a pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. the port debounce is automatically disabled at stop mode and recovered after stop mode release. 4. refer to the port 0 debounce enable register (p0db) for the debounce clock of port 1 and port 5.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 69 9.5 p2 port 9.5.1 p2 port description p2 is 8-bit i/o port. p2 control registers consist of p2 data register (p2), p2 direction register (p2io), p2 pull-up resistor selection register (p2pu) and p2 open-drain selection register (p2od). refer to the port function selection registers for the p2 function selection. 9.5.2 register description for p2 p2 (p2 data register) : 90h 7 6 5 4 3 2 1 0 p27 p26 p25 p24 p23 p22 p21 p20 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p2[7:0] i/o data p2io (p2 direction register) : b9h 7 6 5 4 3 2 1 0 p27io p26io p25io p24io p23io p22io p21io p20io r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p2io[7:0] p2 data i/o direction 0 input 1 output note: ss1 function possible when input p2pu (p2 pull-up resistor selection register) : aeh 7 6 5 4 3 2 1 0 p27pu p26pu p25pu p24pu p23pu p22pu p21pu p20pu r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p2pu[7:0] configure pull-up resistor of p2 port 0 disable 1 enable p2od (p2 open-drain selection register) : 93h 7 6 5 4 3 2 1 0 p27od p26od p25od p24od p23od p22od p21od p20od r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p2od[7:0] configure open-drain of p2 port 0 push-pull output 1 open-drain output
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 70 9.6 p3 port 9.6.1 p3 port description p3 is 8-bit i/o port. p3 control registers consist of p3 data register (p3), p3 direction register (p3io) and p3 pull-up resistor selection register (p3pu). refer to the port function selection registers for the p3 function selection. 9.6.2 register description for p3 p3 (p3 data register) : 98h 7 6 5 4 3 2 1 0 p37 p36 p35 p34 p33 p32 p31 p30 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p3[7:0] i/o data p3io (p3 direction register) : c1h 7 6 5 4 3 2 1 0 p37io p36io p35io p34io p33io p32io p31io p30io r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p3io[7:0] p3 data i/o direction 0 input 1 output p3pu (p3 pull-up resistor selection register) : afh 7 6 5 4 3 2 1 0 p37pu p36pu p35pu p34pu p33pu p32pu p31pu p30pu r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p3pu[7:0] configure pull-up resistor of p3 port 0 disable 1 enable
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 71 9.7 p4 port 9.7.1 p4 port description p4 is 4-bit i/o port. p4 control registers consist of p4 data register (p4), p4 direction register (p4io), p4 pull-up resistor selection register (p4pu) and p4 open-drain selection register (p4od). refer to the port function selection registers for the p4 function selection. 9.7.2 register description for p4 p4 (p4 data register) : a0h 7 6 5 4 3 2 1 0 ? ? ? ? p43 p42 p41 p40 ? ? ? ? r/w r/w r/w r/w initial value : 00h p4[3:0] i/o data p4io (p4 direction register) : c9h 7 6 5 4 3 2 1 0 ? ? ? ? p43io p42io p41io p40io ? ? ? ? r/w r/w r/w r/w initial value : 00h p4io[3:0] p4 data i/o direction 0 input 1 output note: ss0 function possible when input p4pu (p4 pull-up resistor selection register) : a3h 7 6 5 4 3 2 1 0 ? ? ? ? p43pu p42pu p41pu p40pu ? ? ? ? r/w r/w r/w r/w initial value : 00h p4pu[3:0] configure pull-up resistor of p4 port 0 disable 1 enable p4od (p4 open-drain selection register) : 94h 7 6 5 4 3 2 1 0 ? ? ? ? p43od p42od p41od p40od ? ? ? ? r/w r/w r/w r/w initial value : 00h p4od[3:0] configure open-drain of p4 port 0 push-pull output 1 open-drain output
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 72 9.8 p5 port 9.8.1 p5 port description p5 is 6-bit i/o port. p5 control registers consist of p5 data register (p5), p5 direction register (p5io) and p5 pull-up resistor selection register (p5pu) . refer to the port function selection registers for the p5 function selection. 9.8.2 register description for p5 p5 (p5 data register) : b0h 7 6 5 4 3 2 1 0 ? ? p55 p54 p53 p52 p51 p50 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p5[5:0] i/o data p5io (p5 direction register) : d1h 7 6 5 4 3 2 1 0 ? ? p55io p54io p53io p52io p51io p50io ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p5io[5:0] p5 data i/o direction 0 input 1 output note: ec0/eint8/eint10/blnk function possible when input p5pu (p5 pull-up resistor selection register) : 95h 7 6 5 4 3 2 1 0 ? ? p55pu p54pu p53pu p52pu p51pu p50pu ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p5pu[5:0] configure pull-up resistor of p5 port 0 disable 1 enable
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 73 9.9 port function 9.9.1 port function description port function control registers consist of port function selection register 0 ~ 5. (p0fsrh/l ~ p5fsr). 9.9.2 register description for p0fsrh/l ~ p5fsr p0fsrh (port 0 function selection high register) : d3h 7 6 5 4 3 2 1 0 ? ? p0fsrh5 p0fsrh4 p0fsrh3 p0fsrh2 p0fsrh1 p0fsrh0 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p0fsrh[5:4] p07 function select p0fsrh5 p0fsrh4 description 0 0 i/oport (eint5 function possible when input) 0 1 seg22 function 1 0 an5 function 1 1 pwm4cb function p0fsrh[3:2] p06 function select p0fsrh3 p0fsrh2 description 0 0 i/oport (eint4 function possible when input) 0 1 seg23 function 1 0 an4 function 1 1 pwm4ca function p0fsrh[1:0] p05 function select p0fsrh1 p0fsrh0 description 0 0 i/oport (eint3 function possible when input) 0 1 seg24 function 1 0 an3 function 1 1 pwm4bb function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 74 p0fsrl (port 0 function selection low register) : d2h 7 6 5 4 3 2 1 0 ? p0fsrl6 p0fsrl5 p0fsrl4 p0fsrl3 p0fsrl2 p0fsrl1 p0fsrl0 ? r/w r/w r/w r/w r/w r/w r/w initial value : 00h p0fsrl[6:5] p04 function select p0fsrl6 p0fsrl5 description 0 0 i/oport (eint2 function possible when input) 0 1 seg25 function 1 0 an2 function 1 1 pwm4ba function p0fsrl[4:3] p03 function select p0fsrl4 p0fsrl3 description 0 0 i/oport (eint1 function possible when input) 0 1 seg26 function 1 0 an1 function 1 1 pwm4ab function p0fsrl[2:1] p02 function select p0fsrl2 p0fsrl1 description 0 0 i/oport (eint0 function possible when input) 0 1 avref function 1 0 an0 function 1 1 t4o/pwm4a function p0fsrl0 p01 function select 0 i/oport 1 t3o function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 75 p1fsrh (port 1 function selection high register) : d5h 7 6 5 4 3 2 1 0 p1fsrh7 p1fsrh6 p1fsrh5 p1fsrh4 p1fsrh3 p1fsrh2 p1fsrh1 p1fsrh0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p1fsrh[7:6] p17 function select p1fsrh7 p1fsrh6 description 0 0 i/oport (eint6/ss2 function possible when input) 0 1 seg21 function 1 0 an6 function 1 1 not used p1fsrh[5:4] p16 function select p1fsrh5 p1fsrh4 description 0 0 i/oport (eint7 function possible when input) 0 1 seg20 function 1 0 an7 function 1 1 sck2 function p1fsrh[3:2] p15 function select p1fsrh3 p1fsrh2 description 0 0 i/oport 0 1 seg19 function 1 0 an8 function 1 1 miso2 function p1fsrh[1:0] p14 function select p1fsrh1 p0fsrh0 description 0 0 i/oport 0 1 seg18 function 1 0 an9 function 1 1 mosi2 function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 76 p1fsrl (port 1 function selection low register) : d4h 7 6 5 4 3 2 1 0 p1fsrl7 p1fsrl6 p1fsrl5 p1fsrl4 p1fsrl3 p1fsrl2 p1fsrl1 p1fsrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p1fsrl[7:6] p13 function select p1fsrl7 p1fsrl6 description 0 0 i/oport (ec1 function possible when input) 0 1 seg17 function 1 0 an10 function 1 1 buzo function p1fsrl[5:4] p12function select p1fsrl5 p1fsrl4 description 0 0 i/oport (eint11 function possible when input) 0 1 seg16 function 1 0 an11 function 1 1 t1o/pwm1o function p1fsrl[3:2] p11 function select p1fsrl3 p1fsrl2 description 0 0 i/oport (eint12 function possible when input) 0 1 seg15 function 1 0 an12 function 1 1 t2o/pwm2o function p1fsrl[1:0] p10 function select p1fsrl1 p1fsrl0 description 0 0 i/oport 0 1 seg14 function 1 0 an13 function 1 1 rxd1/scl1/miso1 function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 77 p2fsrh (port 2 function selection high register) : d7h 7 6 5 4 3 2 1 0 ? ? ? ? p2fsrh3 p2fsrh2 p2fsrh1 p2fsrh0 ? ? ? ? r/w r/w r/w r/w initial value : 00h p2fsrh3 p27 function select 0 i/oport 1 seg6 function p2fsrh2 p26 function select 0 i/oport 1 seg7 function p2fsrh1 p25 function select 0 i/oport 1 seg8 function p2fsrh0 p24 function select 0 i/oport 1 seg9 function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 78 p2fsrl (port 2 function selection low register) : d6h 7 6 5 4 3 2 1 0 ? ? p2fsrl5 p2fsrl4 p2fsrl3 p2fsrl2 p2fsrl1 p2fsrl0 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p2fsrl5 p23 function select 0 i/oport 1 seg10 function p2fsrl4 p22function select 0 i/oport (ss1 function possible when input) 1 seg11 function p2fsrl[3:2] p21 function select p2fsrl3 p2fsrl2 description 0 0 i/oport 0 1 seg12 function 1 0 an15 function 1 1 sck1 function p2fsrl[1:0] p20 function select p2fsrl1 p1fsrl0 description 0 0 i/oport 0 1 seg13 function 1 0 an14 function 1 1 txd1/sda1/mosi1 function
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 79 p3fsr (port 3 function selection register) : eeh 7 6 5 4 3 2 1 0 p3fsr7 p3fsr6 p3fsr5 p3fsr4 p3fsr3 p3fsr2 p3fsr1 p3fsr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h p3fsr7 p37 function select 0 i/oport 1 com0 function p3fsr6 p36 function select 0 i/oport 1 com1 function p3fsr5 p35 function select 0 i/oport 1 com2/seg0 function p3fsr4 p34 function select 0 i/oport 1 com3/seg1 function p3fsr3 p33 function select 0 i/oport 1 com4/seg2 or com0 function p3fsr2 p32 function select 0 i/oport 1 com5/seg3 or com1 function p3fsr1 p31 function select 0 i/oport 1 com6/seg4 or com2/seg4 function p3fsr0 p30 function select 0 i/oport 1 com7/seg5 or com3/seg5 function notes) 1. the p30-p35 is automatically configured as common or segment signal according to the duty in the lcdcrl register when the pi n is selected as the sub-f unction for common/segment. 2. the com0-com3 signals can be outputted through the p33-p30 pins. refer to the lcd drive control high register (lcdcrh). .
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 80 p4fsr (port 4 function selection register) : efh 7 6 5 4 3 2 1 0 ? p4fsr6 p4fsr5 p4fsr4 p4fsr3 p4fsr2 p4fsr1 p4fsr0 ? r/w r/w r/w r/w r/w r/w r/w initial value : 00h p4fsr6 p43 function select 0 i/oport (ss0 function possible when input) 1 vlc0 function p4fsr[5:4] p42 function select p4fsr5 p4fsr4 description 0 0 i/oport 0 1 vlc1 function 1 0 sck0 function 1 1 not used p4fsr[3:2] p41 function select p4fsr3 p4fsr2 description 0 0 i/oport 0 1 vlc2 function 1 0 txd0/sda0/mosi0 function 1 1 not used p4fsr6[1:0] p40 function select p4fsr1 p4fsr0 description 0 0 i/oport 0 1 vlc3 function 1 0 rxd0/scl0/miso0 function 1 1 not used
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 81 p5fsr (port 5 function selection register) : ffh 7 6 5 4 3 2 1 0 ? ? p5fsr5 p5fsr4 p5fsr3 p5fsr2 p5fsr1 p5fsr0 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h p5fsr5 p54 function select 0 i/oport (eint10 function possible when input) 1 sxout function p5fsr[4:3] p53 function select p5fsr4 p5fsr3 description 0 0 i/oport 0 1 sxin function 1 0 t0o/pwm0o function 1 1 not used p5fsr2 p51 function select 1 0 i/oport 1 1 xin function p5fsr[1:0] p50 function select p5fsr1 p5fsr0 description 0 0 i/oport 0 1 xout function 1 0 not used 1 1 not used note) refer to the configure option for the p55/resetb.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 82 10. interrupt controller 10.1 overview the z51f3220 supports up to 23 interrupt sources. the interrupts have separate enable register bits associated with them, allowing software control. they can also have four levels of priority assigned to them. the non- maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software. the interrupt controller has following features: - receive the request from 23 interrupt source - 6 group priority - 4 priority levels - multi interrupt possibility - if the requests of different priority levels are received simultaneously, the request of higher priority level is served first. - each interrupt source can be controlled by ea bit and each iex bit - interrupt latency: 3~9 machine cycles in single interrupt system the non-maskable interrupt is always enabled. the maskable interrupts are enabled through four pair of interrupt enable registers (ie, ie1, ie2, ie3). each bit of ie, ie1, ie2, ie3 register individually enables/disables the corresponding interrupt source. overall control is provided by bit 7 of ie (ea). when ea is set to ?0?, all interrupts are disabled: when ea is set to ?1?, interrupts are individually enabled or disabled through the other bits of the interrupt enable registers. the ea bit is always cleared to ?0? jumping to an interrupt service vector and set to ?1? executing the [reti] instruction. the z51f3220 supports a four-level priority scheme. each maskable interrupt is individually assigned to one of four priority levels according to ip and ip1. default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-trigger mode. table 10-1 shows the interrupt group priority level that is available for sharing interrupt priority. priority of a group is set by two bits of interrupt priority registers (one bit from ip, another one from ip1). interrupt service routine serves higher priority interrupt first. if two requests of different priority levels are received simultaneously, the request of higher priority level is served prior to the lower one. table 10-1 interrupt group priority level 0 (bit0) interrupt group 1 (bit1) 2 (bit2) 3 (bit3) 4 (bit4) 5 (bit5) interrupt 0 interrupt 6 interrupt 12 interrupt 18 interrupt 1 interrupt 7 interrupt 13 interrupt 19 interrupt 2 interrupt 8 interrupt 14 interrupt 20 interrupt 3 interrupt 9 interrupt 15 interrupt 21 interrupt 4 interrupt 10 interrupt 16 interrupt 22 interrupt 5 interrupt 11 interrupt 17 interrupt 23 highest lowest highest lowest
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 83 10.2 external interrupt the external interrupt on int0, int1, int5, int6 and int11 pins receive various interrupt request depending on the external interrupt polarity 0 high/low register (eipol0h/l) and external interrupt polarity 1 register (eipol1) as shown in figure 10.1. also each external interrupt source has enable/disable bits. the external interrupt flag 0 register (eiflag0) and external interrupt flag 1 register 1 (eiflag1) provides the status of external interrupts. eint1 pin eint3 pin eint5 pin eint7 pin eint0 pin flag0 flag1 eint2 pin flag2 flag3 eint4 pin flag4 flag5 eint6 pin flag6 flag7 eint11 pin flag11 eint12 pin flag12 eipol1 2 2 eipol0h, eipol0l 2 2 2 2 2 2 int1 interrupt int11 interrupt int5 interrupt eint10 pin flag10 2 int0 interrupt eint8 pin flag8 2 int6 interrupt figure 10.1 external interrupt description
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 84 10.3 block diagram 0 0 0 0 priority high 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 priority low ea release stop/sleep eint10 eiflag 1 .1 eiflag 1 .2 eint11 eint1 eiflag 0 .0 eint3 eint5 eint7 eint0 eint2 eint4 eint6 eiflag 0 .1 eiflag 0 .2 eiflag 0 .3 eiflag 0 .4 eiflag 0 .5 eiflag 0 .6 eiflag 0 .7 timer 0 overflow timer 0 timer 1 timer 2 timer 3 ip1 ip ie flag10 flag11 ie2 t0ovifr t0ifr t1ifr t2ifr t3ifr flag0 flag1 flag2 flag3 flag4 flag5 flag6 flag7 eipol1 usi0 i2c usi0 rx usi0 tx ie1 i2c0ifr adc wt wdt bit adcifr wtifr wdtifr bitifr level 0 level 1 level 2 level 3 eipol0h/l usi1 i2c usi1 rx usi1 tx i2c1ifr spi2 spiifr eint12 eiflag 1 .3 flag12 eipol1 ie3 eint8 eiflag 1 .0 flag8 eipol1 timer 4 figure 10.2 block diagram of interrupt notes) 1. the release signal for stop/idle mode may be generated by all interrupt sources which are enabled without reference to the priority level. 2. an interrupt request is delayed while data are written to ie, ie1, ie2, ie3, ip, ip1, and pcon register.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 85 10.4 interrupt vector table the interrupt controller supports 24 interrupt sources as shown in the table 10-2. when interrupt is served, long call instruction (lcall) is executed and program counter jumps to the vector address. all interrupt requests have their own priority order. table 10-2 interrupt vector address table interrupt source symbol interrupt enable bit polarity mask vector address hardware reset resetb 0 0 0 non-maskable 0000h external interrupt 10 int0 ie.0 1 maskable 0003h external interrupt 11 int1 ie.1 2 maskable 000bh usi1 i2c interrupt int2 ie.2 3 maskable 0013h usi1 rx interrupt int3 ie.3 4 maskable 001bh usi1 tx interrupt int4 ie.4 5 maskable 0023h external interrupt 0 - 7 int5 ie.5 6 maskable 002bh external interrupt 8 int6 ie1.0 7 maskable 0033h - int7 ie1.1 8 maskable 003bh usi0 i2c interrupt int8 ie1.2 9 maskable 0043h usi0 rx interrupt int9 ie1.3 10 maskable 004bh usi0 tx interrupt int10 ie1.4 11 maskable 0053h external interrupt 12 int11 ie1.5 12 maskable 005bh t0 overflow interrupt int12 ie2.0 13 maskable 0063h t0 match interrupt int13 ie2.1 14 maskable 006bh t1 match interrupt int14 ie2.2 15 maskable 0073h t2 match interrupt int15 ie2.3 16 maskable 007bh t3 match interrupt int16 ie2.4 17 maskable 0083h t4 interrupt int17 ie2.5 18 maskable 008bh adc interrupt int18 ie3.0 19 maskable 0093h spi 2 interrupt int19 ie3.1 20 maskable 009bh wt interrupt int20 ie3.2 21 maskable 00a3h wdt interrupt int21 ie3.3 22 maskable 00abh bit interrupt int22 ie3.4 23 maskable 00b3h - int23 ie3.5 24 maskable 00bbh for maskable interrupt execution, ea bit must set ?1? and specific interrupt must be enabled by writing ?1? to associated bit in the iex. if an interrupt request is received, the specific interrupt request flag is set to ?1?. and it remains ?1? until cpu accepts interrupt. if the interrupt is served, the interrupt request flag will be cleared automatically. 10.5 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ?0? by a reset or an instruction. interrupt acceptance always generates at last cycle of the instruction. so instead of fetching the current instruction, cpu executes internally lcall instruction and saves the pc at stack. for the interrupt service routine, the interrupt controller gives the address of ljmp instruction to cpu. since the end of the execution of current instruction, it needs 3~9 machine cycles to go to the interrupt service routine. the interrupt service task is terminated by the interrupt return instruction [reti]. once an interrupt request is generated, the following process is performed.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 86 figure 10.3 interrupt vector address table saves pc value in order to continue process again after executing isr ie.ea flag ? 0 1 program counter low byte sp ? sp + 1 m(sp) ? (pcl) 2 program counter high byte sp ? sp + 1 m(sp) ? (pch) 3 interrupt vector address occurrence (interrupt vector address) 4 isr(interrupt service routine) move, execute 5 return from isr reti 6 program counter high byte recovery (pch) ? (sp-1) 7 main program execution 10 program counter low byte recovery (pcl) ? (sp-1) 8 ie.ea flag ? 1 9
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 87 10.6 effective timing after controlling interrupt bit case a) control interrupt enable register (ie, ie1, ie2, ie3) figure 10.4 effective timing of interrupt enable register case b) interrupt flag register figure 10.5 effective timing of interrupt flag register interrupt flag register command next instruction next instruction after executing next instruction, interrupt flag result is effective. interrupt enable register command next instruction next instruction after executing ie set/clear, enable register is effective.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 88 10.7 multi interrupt if two requests of different priority levels are received simultaneously, the request of higher priority level is served first. if more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. however, for special features, multi-interrupt processing can be executed by software. figure 10.6 effective timing of interrupt figure 10.6 shows an example of multi-interrupt processing. while int1 is served, int0 which has higher priority than int1 is occurred. then int0 is served immediately and then the remain part of int1 service routine is executed. if the priority level of int0 is same or lower than int1, int0 will be served after the int1 service has completed. an interrupt service routine may be only interrupted by an interrupt of higher priority and, if two interrupts of different priority occur at the same time, the higher level interrupt will be served first. an interrupt cannot be interrupted by another interrupt of the same or a lower priority level. if two interrupts of the same priority level occur simultaneously, the service order for those interrupts is determined by the scan order. main program service occur int1 interrupt int1 isr occur int0 interrupt int0 isr reti reti
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 89 10.8 interrupt enable accept timing figure 10.7 interrupt response timing diagram 10.9 interrupt service routine address figure 10.8 correspondence between vector table address and the entry address of isp 10.10 saving/restore general-purpose registers figure 10.9 saving/restore process diagram and sample source main task saving register restoring register interrupt service task intxx : push psw push dpl push dph push b push acc interrupt_processing: ? ? pop acc pop b pop dph pop dpl pop psw reti 01h 25h 00b3h 00b4h basic interval timer vector table address 0eh 2eh 0125h 0126h basic interval timer service routine address interrupt latched interrupt goes active system clock max. 4 machine cycle 4 machine cycle interrupt processing : lcall & ljmp interrupt routine
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 90 10.11 interrupt timing figure 10.10 timing chart of interrupt acceptance and interrupt return instruction interrupt sources are sampled at the last cycle of a command. if an interrupt source is detected the lower 8-bit of interrupt vector (int_vec) is decided. m8051w core makes interrupt acknowledge at the first cycle of a command, and executes long call to jump to interrupt service routine. note) command cycle clpx: l=last cycle, 1=1 st cycle or 1 st phase, 2=2 nd cycle or 2 nd phase 10.12 interrupt register overview 10.12.1 interrupt enable register (ie, ie1, ie2, ie3) interrupt enable register consists of global interrupt control bit (ea) and peripheral interrupt control bits. total 24 peripherals are able to control interrupt. 10.12.2 interrupt priority register (ip, ip1) the 24 interrupts are divided into 6 groups which have each 4 interrupt sources. a group can be assigned 4 levels interrupt priority using interrupt priority register. level 3 is the highest priority, while level 0 is the lowest priority. after a reset ip and ip1 are cleared to ?00h?. if interrupts have the same priority level, lower number interrupt is served first. clp2 clp1 c2p1 c1p1 c2p2 c1p2 clp2 interrupt sampled here 8-bit interrupt vector int_src intr_ack last_cyc intr_lcall int_vec proga sclk {8?h00, int_vec}
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 91 10.12.3 external interrupt flag register (eiflag0, eiflag1) the external interrupt flag 0 register (eiflag0) and external interrupt flag 1 register (eiflag1) are set to ?1? when the external interrupt generating condition is satisfied. the flag is cleared when the interrupt service routine is executed. alternatively, the flag can be cleared by writing ?0? to it. 10.12.4 external interrupt polarity re gister (eipol0l, eipol0h, eipol1) the external interrupt polarity 0 high/low register (eipol0h/l) and external interrupt polarity 1 register (eipol1) determines which type of rising/falling/both edge interrupt. initially, default value is no interrupt at any edge.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 92 10.12.5 register map table 10-3 interrupt register map name address dir default description ie a8h r/w 00h interrupt enable register ie1 a9h r/w 00h interrupt enable register 1 ie2 aah r/w 00h interrupt enable register 2 ie3 abh r/w 00h interrupt enable register 3 ip b8h r/w 00h interrupt polarity register ip1 f8h r/w 00h interrupt polarity register 1 eiflag0 c0h r/w 00h external interrupt flag 0 register eipol0l a4h r/w 00h external interrupt polarity 0 low register eipol0h a5h r/w 00h external interrupt polarity 0 high register eiflag1 a6h r/w 00h external interrupt flag 1 register eipol1 a7h r/w 00h external interrupt polarity 1 register 10.13 interrupt register description the interrupt register is used for controlling interrupt functions. also it has external interrupt control registers. the interrupt register consists of interrupt enable register (ie), interrupt enable register 1 (ie1), interrupt enable register 2 (ie2) and interrupt enable register 3 (ie3). for external interrupt, it consists of external interrupt flag 0 register (eiflag0), external interrupt polarity 0 high/low register (eipol0h/l), external interrupt flag 1 register (eiflag1) and external interrupt polarity 1 register (eipol1).
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 93 10.13.1 register description for interrupt ie (interrupt enable register) : a8h 7 6 5 4 3 2 1 0 ea ? int5e int4e int3e int2e int1e int0e r/w ? r/w r/w r/w r/w r/w r/w initial value : 00h ea enable or disable all interrupt bits 0 all interrupt disable 1 all interrupt enable int5e enable or disable external interrupt 0 ~ 7 (eint0 ~ eint7) 0 disable 1 enable int4e enable or disable usi1 tx interrupt 0 disable 1 enable int3e enable or disable usi1 rx interrupt 0 disable 1 enable int2e enable or disable usi1 i2c interrupt 0 disable 1 enable int1e enable or disable external interrupt 11(eint11) 0 disable 1 enable int0e enable or disable external interrupt 10 (eint10) 0 disable 1 enable
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 94 ie1 (interrupt enable register 1): a9h 7 6 5 4 3 2 1 0 ? ? int11e int10e int9e int8e ? int6e ? ? r/w r/w r/w r/w ? r/w initial value: 00h int11e enable or disable external interrupt 12 (eint12) 0 disable 1 enable int10e enable or disable usi0 tx interrupt 0 disable 1 enable int9e enable or disable usi0 rx interrupt 0 disable 1 enable int8e enable or disable usi0 i2c interrupt 0 disable 1 enable int6e enable or disable external interrupt 8 (eint8) 0 disable 1 enable
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 95 ie2 (interrupt enable register 2) : aah 7 6 5 4 3 2 1 0 ?- ? int17e int16e int15e int14e int13e int12e ? ? r/w r/w r/w r/w r/w r/w initial value : 00h int17e enable or disable timer 4 interrupt 0 disable 1 enable int16e enable or disable timer 3 match interrupt 0 disable 1 enable int15e enable or disable timer 2 match interrupt 0 disable 1 enable int14e enable or disable timer 1 match interrupt 0 disable 1 enable int13e enable or disable timer 0 i match nterrupt 0 disable 1 enable int12e enable or disable timer 0 overflow interrupt 0 disable 1 enable ie3 (interrupt enable register 3) : abh 7 6 5 4 3 2 1 0 ? ? ? int22e int21e int20e int19e int18e ? ? ? r/w r/w r/w r/w r/w initial value : 00h int22e enable or disable bit interrupt 0 disable 1 enable int21e enable or disable wdt interrupt 0 disable 1 enable int20e enable or disable wt interrupt 0 disable 1 enable int19e enable or disable spi 2 interrupt 0 disable 1 enable int18e enable or disable adc interrupt 0 disable 1 enable
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 96 ip (interrupt priority register) : b8h 7 6 5 4 3 2 1 0 ? ? ip5 ip4 ip3 ip2 ip1 ip0 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h ip1 (interrupt priority register 1) : f8h 7 6 5 4 3 2 1 0 ? ? ip15 ip14 ip13 ip12 ip11 ip10 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h ip[5:0], ip1[5:0] select interrupt group priority ip1x ipx description 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 97 eiflag0 (external interrupt flag 0 register) : c0h 7 6 5 4 3 2 1 0 flag7 flag6 flag5 flag4 flag3 flag2 flag1 flag0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h eiflag0[7:0] when an external interrupt 0-7 is occurred, the flag becomes ?1?. the flag is cleared only by writing ?0? to the bit. so, the flag should be cleared by software. 0 external interrupt 0 ~ 7 not occurred 1 external interrupt 0 ~ 7 occurred eipol0h (external interrupt polarity 0 high register): a5h 7 6 5 4 3 2 1 0 pol7 pol6 pol5 pol4 r/w r/w r/w r/w r/w r/w r/w r/w initial value: 00h eipol0h[7:0] external interrupt (eint7, eint6, eint5, eint4) polarity selection poln[1:0] description 0 0 no interrupt at any edge 0 1 interrupt on rising edge 1 0 interrupt on falling edge 1 1 interrupt on both of rising and falling edge where n =4, 5, 6 and 7 eipol0l (external interrupt polarity 0 low register): a4h 7 6 5 4 3 2 1 0 pol3 pol2 pol1 pol0 r/w r/w r/w r/w r/w r/w r/w r/w initial value: 00h eipol0l[7:0] external interrupt (eint0, eint1, eint2, eint3) polarity selection poln[1:0] description 0 0 no interrupt at any edge 0 1 interrupt on rising edge 1 0 interrupt on falling edge 1 1 interrupt on both of rising and falling edge where n =0, 1, 2 and 3
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 98 eiflag1 (external interrupt flag 1 register) : a6h 7 6 5 4 3 2 1 0 t0ovifr t0ifr t3ifr ? flag12 flag11 flag10 flag8 r/w r/w r/w ? r/w r/w r/w r/w initial value : 00h t0ovifr when t0 overflow interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or automatically clear by int_ack signal. 0 t0 overflow interrupt no generation 1 t0 overflow interrupt generation t0ifr when t0 interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or automatically clear by int_ack signal. 0 t0 interrupt no generation 1 t0 interrupt generation t3ifr when t3 interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or automatically clear by int_ack signal. 0 t3 interrupt no generation 1 t3 interrupt generation eiflag1[3:0] when an external interrupt (eint8, eint10-eint12) is occurred, the flag becomes ?1?. the flag is cleared by writing ?0? to the bit or automatically cleared by int_ack signal. 0 external interrupt not occurred 1 external interrupt occurred eipol1 (external interrupt polarity 1 register): a7h 7 6 5 4 3 2 1 0 pol12 pol11 pol10 pol8 r/w r/w r/w r/w r/w r/w r/w r/w initial value: 00h eipol1[7:0] external interrupt (eint8,eint10,eint11,eint12) polarity selection poln[1:0] description 0 0 no interrupt at any edge 0 1 interrupt on rising edge 1 0 interrupt on falling edge 1 1 interrupt on both of rising and falling edge where n =8, 10, 11 and 12
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 99 11. peripheral hardware 11.1 clock generator 11.1.1 overview as shown in figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and the peripheral hardware. it contains main/sub-frequency clock oscillator. the main/sub clock operation can be easily obtained by attaching a crystal between the xin/sxin and xout/sxout pin, respectively. the main/sub clock can be also obtained from the external oscillator. in this case, it is necessary to put the external clock signal into the xin/sxin pin and open the xout/sxout pin. the default system clock is 1mhz int-rc oscillator and the default division rate is eight. in order to stabilize system internally, it is used 1mhz int-rc oscillator on por. - calibrated internal rc oscillator (16 mhz ) . int-rc osc/1 (16 mhz) . int-rc osc/2 (8 mhz) . int-rc osc/4 (4 mhz) . int-rc osc/8 (2 mhz) . int-rc osc/16 (1 mhz, default system clock) . int-rc osc/32 (0.5 mhz) - main crystal oscillator (0.4~12 mhz) - sub crystal oscillator (32.768 khz) - internal wdtrc oscillator (5 khz) 11.1.2 block diagram clock change system clock gen. sclk (fx) (core, system, peripheral ) dclk bit wdt bit overflow xin xout main osc f xin stop mode xclke internal rc osc (16mhz) stop mode irce f irc 1/1 1/2 1/4 1/8 m u x wdtrc osc (5khz) wdtck stabilization time generation m u x bit clock wdt clock sxin sxout sub osc f sub stop mode sclke wt 2 sclk[1:0] /256 1/16 1/32 3 ircs[2:0] fx/4096 fx/1024 fx/128 fx/16 m u x 2 bitck[1:0] figure 11.1 clock generator block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 100 11.1.3 register map table 11-1 clock generator register map name address dir default description sccr 8ah r/w 00h system and clock control register osccr c8h r/w 20h oscillator control register 11.1.4 clock generator register description the clock generator register uses clock control for system operation. the clock generation consists of system and clock control register and oscillator control register. 11.1.5 register description for clock generator sccr (system and clock control register) : 8ah 7 6 5 4 3 2 1 0 ? ? ? ? ? ? sclk1 sclk0 ? ? ? ? ? ? r/w r/w initial value : 00h sclk [1:0] system clock selection bit sclk1 sclk0 description 0 0 int rc osc (f irc ) for system clock 0 1 external main osc (f xin ) for system clock 1 0 external sub osc (f sub ) for system clock 1 1 not used
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 101 osccr (oscillator control register) : c8h 7 6 5 4 3 2 1 0 ? ? ircs2 ircs1 ircs0 irce xclke sclke ? ? r/w r/w r/w r/w r/w r/w initial value : 08h ircs[2:0] internal rc oscillator post-divider selection ircs2 ircs1 ircs0 description 0 0 0 int-rc/32 (0.5mhz) 0 0 1 int-rc/16 (1mhz) 0 1 0 int-rc/8 (2mhz) 0 1 1 int-rc/4 (4mhz) 1 0 0 int-rc/2 (8mhz) 1 0 1 int-rc/1 (16mhz) other values not used irce control the operation of the internal rc oscillator 0 enable operation of int-rc osc 1 disable operation of int-rc osc xclke control the operation of the external main oscillator 0 disable operation of x-tal 1 enable operation of x-tal sclke control the operation of the external sub oscillator 0 disable operation of sx-tal 1 enable operation of sx-tal
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 102 11.2 basic interval timer 11.2.1 overview the z51f3220 has one 8-bit basic interval timer that is free-run and can?t stop. block diagram is shown in figure 11.2. in addition, the basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (bitifr). the z51f3220 has these basic interval timer (bit) features: - during power on, bit gives a stable clock generation time - on exiting stop mode, bit gives a stable clock generation time - as timer function, timer interrupt occurrence 11.2.2 block diagram bit clock bck[2 :0] 8 -bit up counter bitcnt bclr clear bitifr to interrupt block selected bit overflow wdt int_ack clear start cpu reset stop figure 11.2 basic interval timer block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 103 11.2.3 register map table 11-2 basic interval timer register map name address dir default description bitcnt 8ch r 00h basic interv al timer counter register bitcr 8bh r/w 01h basic interval timer control register 11.2.4 basic interval timer register description the basic interval timer register consists of basic interval timer counter register (bitcnt) and basic interval timer control register (bitcr). if bclr bit is set to ?1?, bitcnt becomes ?0? and then counts up. after 1 machine cycle, bclr bit is cleared to ?0? automatically. 11.2.5 register description for basic interval timer bitcnt (basic interval timer counter register) : 8ch 7 6 5 4 3 2 1 0 bitcnt7 bitcnt6 bitcnt5 bitcnt4 bitcnt3 bitcnt2 bitcnt1 bitcnt0 r r r r r r r r initial value : 00h bitcnt[7:0] bit counter
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 104 bitcr (basic interval timer control register) : 8bh 7 6 5 4 3 2 1 0 bitifr bitck1 bitck0 ? bclr bck2 bck1 bck0 r/w r/w r/w ? r/w r/w r/w r/w initial value : 01h bitifr when bit interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or auto clear by int_ack signal. 0 bit interrupt no generation 1 bit interrupt generation bitck[1:0] select bit clock source bitck1 bitck0 description 0 0 fx/4096 0 1 fx/1024 1 0 fx/128 1 1 fx/16 bclr if this bit is written to ?1?, bit counter is cleared to ?0? 0 free running 1 clear counter bck[2:0] select bit overflow period bck2 bck1 bck0 description 0 0 0 bit 0 overflow (bit clock * 2) 0 0 1 bit 1 overflow (bit clock * 4) (default) 0 1 0 bit 2 overflow (bit clock * 8) 0 1 1 bit 3 overflow (bit clock * 16) 1 0 0 bit 4 overflow (bit clock * 32) 1 0 1 bit 5 overflow (bit clock * 64) 1 1 0 bit 6 overflow (bit clock * 128) 1 1 1 bit 7 overflow (bit clock * 256)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 105 11.3 watch dog timer 11.3.1 overview the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or something like that, and resumes the cpu to the normal state. the watchdog timer signal for malfunction detection can be used as either a cpu reset or an interrupt request. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. it is possible to use free running 8- bit timer mode (wdtrson=?0?) or watch dog timer mode (wdtrson=?1?) as setting wdtcr[6] bit. if wdtcr[5] is written to ?1?, wdt counter value is cleared and counts up. after 1 machine cycle, this bit is cleared to ?0? automatically. the watchdog timer consists of 8-bit binary counter and the watchdog timer data register. when the value of 8-bit binary counter is equal to the 8 bits of wdtcnt, the interrupt request flag is generated. this can be used as watchdog timer interrupt or reset of cpu in accordance with the bit wdtrson. the input clock source of watch dog timer is the bit overflow. the interval of watchdog timer interrupt is decided by bit overflow period and wdtdr set value. the equation can be described as wdt interrupt interval = (bit interrupt interval) x (wdtdr value+1) 11.3.2 wdt interrupt timing waveform figure 11.3 watch dog timer interrupt timing waveform source clock bit overflow wdtcnt[7:0] wdtdr[7:0] wdtifr interrupt wdtresetb wdtcl occur wdtdr ? 0000_0011b match detect counter clear reset 0 1 2 3 0 1 2 3 0 1 2 n 3
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 106 11.3.3 block diagram wdtcnt wdt clock clear wdtdr wdtcr wdtcl wdtrson wdten to reset circuit wdtifr to interrupt block int_ack clear figure 11.4 watch dog timer block diagram 11.3.4 register map table 11-3 watch dog timer register map name address dir default description wdtcnt 8eh r 00h watch do g timer counter register wdtdr 8eh w ffh watch dog timer data register wdtcr 8dh r/w 00h watch dog timer control register 11.3.5 watch dog timer register description the watch dog timer register consists of watch dog timer counter register (wdtcnt), watch dog timer data register (wdtdr) and watch dog timer control register (wdtcr).
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 107 11.3.6 register description for watch dog timer wdtcnt (watch dog timer counter register: read case) : 8eh 7 6 5 4 3 2 1 0 wdtcnt 7 wdtcnt 6 wdtcnt 5 wdtcnt 4 wdtcnt3 wdtcnt 2 wdtcnt 1 wdtcnt 0 r r r r r r r r initial value : 00h wdtcnt[7:0] wdt counter wdtdr (watch dog timer data register: write case) : 8eh 7 6 5 4 3 2 1 0 wdtdr7 wdtdr 6 wdtdr 5 wdtdr 4 wdtdr 3 wdtdr 2 wdtdr 1 wdtdr 0 w w w w w w w w initial value : ffh wdtdr[7:0] set a period wdt interrupt interval=(bit interrupt interval) x(wdtdr value+1) note) do not write ?0? in the wdtdr register. wdtcr (watch dog timer control register) : 8dh 7 6 5 4 3 2 1 0 wdten wdtrson wdtcl ? ? ? wdtck wdtifr r/w r/w r/w ? ? ? r/w r/w initial value : 00h wdten control wdt operation 0 disable 1 enable wdtrson control wdt reset operation 0 free running 8-bit timer 1 watch dog timer reset on wdtcl clear wdt counter 0 free run 1 clear wdt counter (auto clear after 1 cycle) wdtck control wdt clock selection bit 0 bit overflow for wdt clock (wdtrc disable) 1 wdtrc for wdt xlock (wdtrc enable) wdtifr when wdt interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or auto clear by int_ack signal. 0 wdt interrupt no generation 1 wdt interrupt generation
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 108 11.4 watch timer 11.4.1 overview the watch timer has the function for rtc (real time clock) operation. it is generally used for rtc design. the internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register. to operate the watch timer, determine the input clock source, output interval, and set wten to ?1? in watch timer control register (wtcr). it is able to execute simultaneously or individually. to stop or reset wt, clear the wten bit in wtcr register. even if cpu is stop mode, sub clock is able to be so alive that wt can continue the operation. the watch timer counter circuits may be composed of 21- bit counter which contains low 14-bit with binary counter and high 7-bit counter in order to raise resolution. in wtdr, it can control wt clear and set interval value at write time, and it can read 7-bit wt counter value at read time. the watch timer supplies the clock frequency for the lcd driver (f lcd ). therefore, if the watch timer is disabled, the lcd driver controller does not operate. 11.4.2 block diagram p r e s c a l e r fx m u x f sub f wck 14bit binary counter timer counter f wck /2 14 wtcr wten -- wtifr wtin1 wtin0 wtck1 wtck0 mux f wck /2 14 f wck /2 13 f wck /2 7 wtifr to interrupt block wtcl wtdr6 wtdr5 wtdr4 wtdr3 wtdr2 wtdr1 wtdr0 wtdr write case - wtcnt6 wtcnt5 wtcnt4 wtcnt3 wtcnt2 wtcnt1 wtcnt0 wtcnt read case clear int_ack fx/64 fx/128 fx/256 f lcd =1024 hz 2 f wck 14 /(2 x (7 bit wtdr value +1)) comparator match reload match wtcl clear match wtcl figure 11.5 watch timer block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 109 11.4.3 register map table 11-4 watch timer register map name address dir default description wtcnt 89h r 00h watch timer counter register wtdr 89h w 7fh watch timer data register wtcr 96h r/w 00h watch timer control register 11.4.4 watch timer register description the watch timer register consists of watch timer counter register (wtcnt), watch timer data register (wtdr), and watch timer control register (wtcr). as wtcr is 6-bit writable/ readable register, wtcr can control the clock source (wtck[1:0]), interrupt interval (wtin[1:0]), and function enable/disable (wten). also there is wt interrupt flag bit (wtifr). 11.4.5 register description for watch timer wtcnt (watch timer counter register: read case) : 89h 7 6 5 4 3 2 1 0 ? wtcnt 6 wtcnt 5 wtcnt 4 wtcnt 3 wtcnt 2 wtcnt 1 wtcnt0 ? r r r r r r r initial value : 00h wtcnt[6:0] wt counter wtdr (watch timer data register: write case) : 89h 7 6 5 4 3 2 1 0 wtcl wtdr 6 wtdr 5 wtdr 4 wtdr 3 wtdr 2 wtdr 1 wtdr 0 r/w w w w w w w w initial value : 7fh wtcl clear wt counter 0 free run 1 clear wt counter (auto clear after 1 cycle) wtdr[6:0] set wt period wt interrupt interval=fwck/(2^14 x(7bit wtdr value+1)) note) do not write ?0? in the wtdr register.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 110 wtcr (watch timer control register) : 96h 7 6 5 4 3 2 1 0 wten ? ? wtifr wtin1 wtin0 wtck1 wtck0 r/w ? ? r/w r/w r/w r/w r/w initial value : 00h wten control watch timer 0 disable 1 enable wtifr when wt interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or automatically clear by int_ack signal. 0 wt interrupt no generation 1 wt interrupt generation wtin[1:0] determine interrupt interval wtin1 wtin0 description 0 0 f wck /2^7 0 1 f wck /2^13 1 0 f wck /2^14 1 1 f wck /(2^14 x (7bit wtdr value+1)) wtck[1:0] determine source clock wtck1 wtck0 description 0 0 f sub 0 1 f x /256 1 0 f x /128 1 1 f x /64 note) f x ? system clock frequency (where fx= 4.19mhz) f sub ? sub clock oscillator frequency (32.768khz) f wck ? selected watch timer clock f lcd ? lcd frequency (where f x = 4.19mhz, wtck[1:0]=?10?; f lcd = 1024hz)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 111 11.5 timer 0 11.5.1 overview the 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (t0cnt, t0dr, t0cdr, t0cr). it has three operating modes: - 8-bit timer/counter mode - 8-bit pwm output mode - 8-bit capture mode the timer/counter 0 can be clocked by an internal or an external clock source (ec0). the clock source is selected by clock selection logic which is controlled by the clock selection bits (t0ck[2:0]). - timer 0 clock source: f x /2, 4, 8, 32, 128, 512, 2048 and ec0 in the capture mode, by eint10, the data is captured into input capture data register (t0cdr). in timer/counter mode, whenever counter value is equal to t0dr, t0o port toggles. also the timer 0 outputs pwm waveform through pwm0o port in the pwm mode. table 11-5 timer 0 operating modes t0en t0ms[1:0] t0ck[2:0] timer 0 1 00 xxx 8 bit timer/counter mode 1 01 xxx 8 bit pwm mode 1 1x xxx 8 bit capture mode
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 112 11.5.2 8-bit timer/counter mode the 8-bit timer/counter mode is selected by control register as shown in figure 11.6. the 8-bit timer have counter and data register. the counter register is increased by internal or external clock input. timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (t0ck[2:0]). when the value of t0cnt and t0dr is identical in timer 0, a match signal is generated and the interrupt of timer 0 occurs. t0cnt value is automatically cleared by match signal. it can be also cleared by software (t0cc). the external clock (ec0) counts up the timer at the rising edge. if the ec0 is selected as a clock source by t0ck[2:0], ec0 port should be set to the input port by p52io bit. p r e s c a l e r fx m u x fx/2 t0cnt(8bit) ec0 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t0ck[2:0] t0 en 8-bit timer 0 counter t0dr(8bit) comparator t0ifr t0 o/pw m 0o 8-bit timer 0 data register int_ack clear match signal clear match mux t0ms[1:0] 2 to interrupt block t0en - t0ms1 t0ms0 t0ck2 t0ck1 t0ck0 t0cc t0cr 1 -00xxxx address : b2h initial value: 0000 _0000b t0 c c figure 11.6 8-bit timer/counter mode for timer 0 figure 11.7 8-bit timer/counter 0 example t0cnt v alue timer 0 (t0ifr) interrupt time 1 2 3 4 5 6 n-2 n-1 n interrupt period = p cp x (n+1) 0 count pulse period p cp up-count match with t0dr occur interrupt occur interrupt occur interrupt
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 113 11.5.3 8-bit pwm mode the timer 0 has a high speed pwm (pulse width modulation) function. in pwm mode, t0o/pwm0o pin outputs up to 8-bit resolution pwm output. this pin should be configured as a pwm output by setting the t0o/pwm0o function by p5fsr[4:3] bits. in the 8-bit timer/counter mode, a match signal is generated when the counter value is identical to the value of t0dr. when the value of t0cnt and t0dr is identical in timer 0, a match signal is generated and the interrupt of timer 0 occurs. in pwm mode, the match signal does not clear the counter. instead, it runs continuously, overflowing at ?ffh?, and then continues incrementing from ?00h?. the timer 0 overflow interrupt is generated whenever a counter overflow occurs. t0cnt value is cleared by software (t0cc) bit. p r e s c a l e r fx m u x fx/2 t0cnt(8bit) ec0 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t0ck[2:0] t0 en 8-bit timer 0 counter t0dr(8bit) comparator t0ifr t0 o/pw m 0o 8-bit timer 0 data register int_ack clear clear match mux t0ovifr clear t0ms[1:0] 2 int_ack to interrupt block to interrupt block t0en - t0ms1 t0ms0 t0ck2 t0ck1 t0ck0 t0cc t0cr 1 -01xxxx address : b2h initial value: 0000 _0000b match signal t0 c c figure 11.8 8-bit pwm mode for timer 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 114 xx t0cnt t0pwm 00h 01h 02h 4ah ffh feh 00h t0 match interrupt t0 overflow interrupt t0dr 1. t0dr = 4ah timer 0 clock set t0en t0pwm t0 match interrupt 2. t0dr = 00h t0pwm t0 match interrupt 3. t0dr = ffh pwm mode(t0ms = 01b) figure 11.9 pwm output waveforms in pwm mode for timer 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 115 11.5.4 8-bit capture mode the timer 0 capture mode is set by t0ms[1:0] as ?1x?. the clock source can use the internal/external clock. basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when t0cnt is equal to t0dr. t0cnt value is automatically cleared by match signal and it can be also cleared by software (t0cc). this timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. the capture result is loaded into t0cdr. in the timer 0 capture mode, timer 0 output (t0o) waveform is not available. according to eipol1 registers setting, the external interrupt eint10 function is chosen. of cource, the eint10 pin must be set to an input port. t0cdr and t0dr are in the same address. in the capture mode, reading operation reads t0cdr, not t0dr and writing operation will update t0dr. p r e s c a l e r fx m u x fx/2 t0cnt(8bit) ec0 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t0ck[2:0] t0 en 8-bit timer 0 counter t0dr(8bit) comparator t0ifr 8-bit timer 0 data register int_ack clear match mux t0cdr(8bit) clear flag10 (eiflag 1.0 ) 2 t0ms[1:0] 2 t0 m s[1 :0] int_ack clear to interrupt block to interrupt block t0en - t0ms1 t0ms0 t0ck2 t0ck1 t0ck0 t0cc t0cr 1 -1xxxxx address : b2h initial value: 0000 _0000b clear eint10 eipol1[1:0] 2 match signal t0 c c figure 11.10 8-bit capture mode for timer 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 116 figure 11.11 input capture mode operation for timer 0 figure 11.12 express timer overflow in capture mode t0cnt interrupt request (flag10) x x h interrupt interval period = ff h +01 h +ff h +01 h +yy h +01 h ext. eint10 pin interrupt request (t0ifr) ff h ff h yy h 00 h 00 h 00 h 00 h 00 h t0cnt value interrupt request (flag10) time 1 2 3 4 5 6 n-2 n-1 n interrupt interval period 0 count pulse period p cp up-count t0cdr load ext. eint10 pin
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 117 11.5.5 block diagram int_ack p r e s c a l e r fx m u x fx/2 t0cnt (8bit) ec0 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t0ck[2:0] t0 en 8-bit timer 0 counter t0dr (8bit) comparator t0ifr to interrupt block t0o/pwm0o 8-bit timer 0 data register int_ack clear clear match mux t0cdr (8bit) clear t0 ovi f r to interrupt block clear eint10 eipol 1[1 :0] flag10 (eiflag1.0) int_ack clear to interrupt block 2 t 0m s[1 :0] 2 t0ms[1:0] 2 match signal t0cc figure 11.13 8-bit timer 0 block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 118 11.5.6 register map table 11-6 timer 0 register map name address dir default description t0cnt b3h r 00h timer 0 counter register t0dr b4h r/w ffh timer 0 data register t0cdr b4h r 00h timer 0 capture data register t0cr b2h r/w 00h timer 0 control register 11.5.6.1 timer/counter 0 register description the timer/counter 0 register consists of timer 0 counter register (t0cnt), timer 0 data register (t0dr), timer 0 capture data register (t0cdr), and timer 0 control register (t0cr). t0ifr and t0ovifr bits are in the external interrupt flag 1 register (eiflag1). 11.5.6.2 register description for timer/counter 0 t0cnt (timer 0 counter register) : b3h 7 6 5 4 3 2 1 0 t0cnt7 t0cnt6 t0cnt5 t0cnt4 t0cnt3 t0cnt2 t0cnt1 t0cnt0 r r r r r r r r initial value : 00h t0cnt[7:0] t0 counter t0dr (timer 0 data register) : b4h 7 6 5 4 3 2 1 0 t0dr7 t0dr6 t0dr5 t0dr4 t0dr3 t0dr2 t0dr1 t0dr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t0dr[7:0] t0 data t0cdr (timer 0 capture data register: read case, capture mode only) : b4h 7 6 5 4 3 2 1 0 t0cdr7 t0cdr6 t0cdr5 t0cdr4 t0cdr3 t0cdr2 t0cdr1 t0cdr0 r r r r r r r r initial value : 00h t0cdr[7:0] t0 capture data
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 119 t0cr (timer 0 control register) : b2h 7 6 5 4 3 2 1 0 t0en ? t0ms1 t0ms0 t0ck2 t0ck1 t0ck0 t0cc r/w ? r/w r/w r/w r/w r/w r/w initial value : 00h t0en control timer 0 0 timer 0 disable 1 timer 0 enable t0ms[1:0] control timer 0 operation mode t0ms1 t0ms0 description 0 0 timer/counter mode 0 1 pwm mode 1 x capture mode t0ck[2:0] select timer 0 clock source. fx is a system clock frequency t0ck2 t0ck1 t0ck0 description 0 0 0 fx/2 0 0 1 fx/4 0 1 0 fx/8 0 1 1 fx/32 1 0 0 fx/128 1 0 1 fx/512 1 1 0 fx/2048 1 1 1 external clock (ec0) t0cc clear timer 0 counter 0 no effect 1 clear the timer 0 counter (when write, automatically cleared ?0? after being cleared counter) notes) 1. match interrupt is generated in capture mode. 2. refer to the external interrupt flag 1 register (eiflag1) for the t0 interrupt flags.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 120 11.6 timer 1 11.6.1.1 overview the 16-bit timer 1 consists of multiplexer, timer 1 a data register high/low, timer 1 b data register high/low and timer 1 control register high/low (t1adrh, t1adrl, t1bdrh, t1bdrl , t1crh, t1crl). it has four operating modes: - 16-bit timer/counter mode - 16-bit capture mode - 16-bit ppg output mode (one-shot mode) - 16-bit ppg output mode (repeat mode) the timer/counter 1 can be clocked by an internal or an external clock source (ec1). the clock source is selected by clock selection logic which is controlled by the clock selection bits (t1ck[2:0]). - timer 1 clock source: f x /1, 2, 4, 8, 64, 512, 2048 and ec1 in the capture mode, by eint11, the da ta is captured into input capture data register (t1bdrh/t1bdrl). timer 1 outputs the comparision result between counter and data register through t1o port in timer/counter mode. also ttimer 1 outputs pwm wave form through pwm1o port in the ppg mode. table 11-7 timer 1 operating modes t1en p1fsrl[5:4] t1ms[1 :0] t1ck[2:0] timer 1 1 11 00 xxx 16 bit timer/counter mode 1 00 01 xxx 16 bit capture mode 1 11 10 xxx 16 bit ppg mode (one-shot mode) 1 11 11 xxx 16 bit ppg mode (repeat mode) 11.6.2 16-bit timer/counter mode the 16-bit timer/counter mode is selected by control register as shown in figure 11.14. the 16-bit timer have counter and data register. the counter register is increased by internal or external clock input. timer 1 can use the input clock with one of 1, 2, 4, 8, 64, 512 and 2048 prescaler division rates (t1ck[2:0]). when the value of t1cnth, t1cntl and the value of t1adrh, t1adrl are identical in timer 1 respectively, a match signal is generated and the interrupt of timer 1 occurs. the t1cnth, t1cntl value is automatically cleared by match signal. it can be also cleared by software (t1cc). the external clock (ec1) counts up the timer at the rising edge. if the ec1 is selected as a clock source by t1ck[2:0], ec1 port should be set to the input port by p13io bit.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 121 t1 en t1crh 1 address:bbh initial value : 0000 _0000 b t 1m s[1 :0] t 1pol a match t1 c c t1 en p r e s c a l e r fx m u x fx/2 fx/4 fx/64 fx/512 fx/2048 fx/8 fx/1 16- bit counter t1cnth/t1cntl clear edge detector t1ec e ec1 comparator 16-bit a data register t1adrh/t1adrl t1ifr int_ack clear to interrupt block a match buffer register a a match t1c c reload pulse generator t1o r t1 en 3 t1 c k[2: 0] 2 C t1 m s1 t 1m s0 CC C t1cc C 00 CC Cx t1ck2 t1crl x address:bah initial value : 0000 _0000 b t1 c k1 t 1c k0 t 1i f r C t1pol t1ece t1cntr xxx C xx x t1en figure 11.14 16-bit timer/counter mode for timer 1 figure 11.15 16-bit timer/counter 1 example t1cnth/l v alue timer 1 (t1ifr) interrupt time 1 2 3 4 5 6 n-2 n-1 n interrupt period = p cp x (n+1) 0 count pulse period p cp up-count match with t1adrh/l occur interrupt occur interrupt occur interrupt
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 122 11.6.3 16-bit capture mode the 16-bit timer 1 capture mode is set by t1ms[1:0] as ?01?. the clock source can use the internal/external clock. basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when t1cnth/t1cntl is equal to t1adrh/t1adrl. the t1cnth, t1cntl values are automatically cleared by match signal. it can be also cleared by software (t1cc). this timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. the capture result is l oaded into t1 bdrh/t1bdrl. according to eipol1 registers setting, the external interrupt eint11 function is chosen. of cource, the eint11 pin must be set as an input port. a match t1 c c t1 en p r e s c a l e r fx m u x fx/2 fx/4 fx/64 fx/512 fx/2048 fx/8 fx/1 16- bit counter t1cnth/t1cntl 16-bit b data register t1bdrh/t1bdrl clear edge detector t1ec e ec1 comparator 16-bit a data register t1adrh/t1adrl t1ifr int_ack clear to interrupt block a match buffer register a a match t1c c reload r eint11 t1cntr t1 en 3 t1 c k[2: 0] clear eipolb[1:0] flag11 (eiflag1.2) int_ack clear to interrupt block 2 t1ms[1:0] 2 t1en t1c r h 1 address:bbh initial value : 0000 _0000b C t1m s1 t 1m s0 CCC t1cc C 01 CCC x t1ck1 t1crl x address:bah initial value : 0000 _0000b t1ck1 t1ck0 t1ifr C t1pol t1ece t1cntr xxx C xxx t1en figure 11.16 16-bit capture mode for timer 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 123 figure 11.17 input capture mode operation for timer 1 figure 11.18 express timer overflow in capture mode t1cnth/l interrupt request (flag11) x x h interrupt interval period = ffff h +01 h +ffff h +01 h +yy h +01 h ext. eint11 pin interrupt request (t1ifr) ffff h ffff h yy h 00 h 00 h 00 h 00 h 00 h t1cnth/l v alue interrupt request (flag11) time 1 2 3 4 5 6 n-2 n-1 n interrupt interval period 0 count pulse period p cp up-count t1bdrh/l load ext. eint11 pin
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 124 11.6.4 16-bit ppg mode the timer 1 has a ppg (programmable pulse generation) function. in ppg mode, t1o/pwm1o pin outputs up to 16-bit resolution pwm output. this pin should be configured as a pwm output by setting p1fsrl[5:4] to ?11? . the period of the pwm output is determined by the t1adrh/t1adrl. and the duty of the pwm output is determined by the t1bdrh/t1bdrl. t 1m s[1 :0] t1pol reload a match t1 c c t1 en p r e s c a l e r fx m u x fx/2 fx/4 fx/64 fx/512 fx/2048 fx/8 fx/1 comparator 16- bit counter t1cnth/t1cntl 16-bit b data register t1bdrh/t1bdrl clear b match edge detector t1ec e ec1 buffer register b comparator 16-bit a data register t1adrh/t1adrl t1ifr int_ack clear to interrupt block a match buffer register a reload pulse generator t1o/ pwm1o r t1 en 3 t1 c k[2: 0] 2 t1en t1 c r h 1 address:bbh initial value : 0000 _0000 b C t1m s1 t 1m s0 CCC t1cc C 11 CCC x t1ck2 t1c r l x address:bah initial value : 0000 _0000 b t1c k1 t 1c k0 t 1i f r C t1pol t1ece t1cntr xxx C xxx a match t1cc t1en a match t1cc t1en note) the t1en is automatically cleared to logic ?0? after one pulse is generated at a ppg one-shot mode. figure 11.19 16-bit ppg mode for timer 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 125 x124568m - 1m023 timer 1 clock counter t1adrh/l t1 interrupt pwm1o b match repeat mode(t1ms = 11b) and "start high"(t1pol = 0b). set t1en 0 clear and start 37 1 m a match 1. t1bdrh/l(5) < t1adrh/l pwm1o a match 2. t1bdrh/l >= t1adrh/l pwm1o a match 3. t1bdrh/l = "0000h" low level x124568m - 1m0 timer 1 clock counter t1adrh/l t1 interrupt pwm1o b match one-shot mode(t1ms = 10b) and "start high"(t1pol = 0b). set t1en 0 clear and start 37 m a match 1. t1bdrh/l(5) < t1adrh/l pwm1o a match 2. t1bdrh/l >= t1adrh/l pwm1o a match 3. t1bdrh/l = "0000h" low level figure 11.20 16-bit ppg mode timming chart for timer 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 126 11.6.5 block diagram t1ms[ 1:0] t 1pol reload a match t1cc t1en p r e s c a l e r fx m u x fx/2 fx/4 fx/64 fx/512 fx/2048 fx/8 fx/1 comparator 16-bit counter t1cnth/t1cntl 16-bit b data register t1bdrh/t1bdrl clear b match buffer register b comparator 16-bit a data register t1adrh/t1adrl t1ifr int_ack clear to interrupt block a match buffer register a reload pulse generator t1o/ pwm1o r eint11 t1cntr t1en 3 t1ck[2:0] clear eipol1 [5:4] flag11 (eiflag1 .2) int_ack clear to interrupt block 2 2 t1ms[1:0] 2 edge detector t1ec e ec1 to timer 2 block a match t1cc t1en a match t1cc t1en figure 11.21 16-bit timer/counter mode for timer 1 and block diagram 11.6.6 register map table 11-8 timer 2 register map name address dir default description t1adrh bdh r/w ffh timer 1 a data high register t1adrl bch r/w ffh timer 1 a data low register t1bdrh bfh r/w ffh timer 1 b data high register t1bdrl beh r/w ffh timer 1 b data low register t1crh bbh r/w 00h timer 1 control high register t1crl bah r/w 00h timer 1 control low register
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 127 11.6.6.1 timer/counter 1 register description the timer/counter 1 register consists of timer 1 a data high register (t1adrh), timer 1 a data low register (t1adrl), timer 1 b data high register (t1bdrh), timer 1 b data low register (t1bdrl), timer 1 control high register (t1crh) and timer 1 co ntrol low register (t1crl). 11.6.6.2 register description for timer/counter 1 t1adrh (timer 1 a data high register) : bdh 7 6 5 4 3 2 1 0 t1adrh7 t1adrh6 t1adrh5 t1adrh4 t1adrh3 t1adrh2 t1adrh1 t1adrh0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t1adrh[7:0] t1 a data high byte t1adrl (timer 1 a data low register) : bch 7 6 5 4 3 2 1 0 t1adrl7 t1adrl6 t1adrl5 t1adrl4 t1adrl3 t1adrl2 t1adrl1 t1adrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t1adrl[7:0] t1 a data low byte note) do not write ?0000h? in the t1adrh/t1adrl register when ppg mode t1bdrh (timer 1 b data high register) : bfh 7 6 5 4 3 2 1 0 t1bdrh7 t1bdrh6 t1bdrh5 t1bdrh4 t1bdrh3 t1bdrh2 t1bdrh1 t1bdrh0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t1bdrh[7:0] t1 b data high byte t1bdrl (timer 1 b data low register) : beh 7 6 5 4 3 2 1 0 t1bdrl7 t1bdrl6 t1bdrl5 t1bdrl4 t1bdrl3 t1bdrl2 t1bdrl1 t1bdrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t1bdrl[7:0] t1 b data low byte
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 128 t1crh (timer 1 control high register) : bbh 7 6 5 4 3 2 1 0 t1en ? t1ms1 t1ms0 ? ? ? t1cc r/w ? r/w r/w ? ? ? r/w initial value : 00h t1en control timer 1 0 timer 1 disable 1 timer 1 enable (counter clear and start) t1ms[1:0] control timer 1 operation mode t1ms1 t1ms0 description 0 0 timer/counter mode (t1o: toggle at a match) 0 1 capture mode (the a match interrupt can occur) 1 0 ppg one-shot mode (pwm1o) 1 1 ppg repeat mode (pwm1o) t1cc clear timer 1 counter 0 no effect 1 clear the timer 1 counter (when write, automatically cleared ?0? after being cleared counter)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 129 t1crl (timer 1 control low register) : bah 7 6 5 4 3 2 1 0 t1ck2 t1ck1 t1ck0 t1ifr ? t1pol t1ece t1cntr r/w r/w r/w r/w ? r/w r/w r/w initial value : 00h t1ck[2:0] select timer 1 clock source. fx is main system clock frequency t1ck2 t1ck1 t1ck0 description 0 0 0 fx/2048 0 0 1 fx/512 0 1 0 fx/64 0 1 1 fx/8 1 0 0 fx/4 1 0 1 fx/2 1 1 0 fx/1 1 1 1 external clock (ec1) t1ifr when t1 interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or auto clear by int_ack signal. 0 t1 interrupt no generation 1 t1 interrupt generation t1pol t1o/pwm1o polarity selection 0 start high (t1o/pwm1o is low level at disable) 1 start low (t1o/pwm1o is high level at disable) t1ece timer 1 external clock edge selection 0 external clock falling edge 1 external clock rising edge t1cntr timer 1 counter read control 0 no effect 1 load the counter value to the b data register (when write, automatically cleared ?0? after being loaded)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 130 11.7 timer 2 11.7.1.1 overview the 16-bit timer 2 consists of multiplexer, timer 2 a data high/low register, timer 2 b data high/low register and timer 2 control high/low regi ster (t2adrh, t2adrl, t2bdrh , t2bdrl, t2crh, t2crl). it has four operating modes: - 16-bit timer/counter mode - 16-bit capture mode - 16-bit ppg output mode (one-shot mode) - 16-bit ppg output mode (repeat mode) the timer/counter 2 can be divided clock of the system clock selectd from prescaler output and t1 a match (timer 1 a match signal). the clock source is selected by clock selection logic which is controlled by the clock selection bits (t2ck[2:0]). - timer 2 clock source: f x /1, 2, 4, 8, 32, 128, 512 and t1 a match in the capture mode, by eint12, the data is captured into input captur e data register (t2bdrh/t2bdrl). in timer/counter mode, whenever counter value is equal to t2adrh/l, t2 o port toggles. also the timer 2 outputs pwm wave form to pwm2o port in the ppg mode. table 11-9 timer 2 operating modes t2en p1fsrl[3:2] t2ms[1:0] t2ck[2:0] timer 2 1 11 00 xxx 16 bit timer/counter mode 1 00 01 xxx 16 bit capture mode 1 11 10 xxx 16 bit ppg mode (one-shot mode) 1 11 11 xxx 16 bit ppg mode (repeat mode)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 131 11.7.2 16-bit timer/counter mode the 16-bit timer/counter mode is selected by control register as shown in figure 11.22. the 16-bit timer have counter and data register. the counter register is increased by internal or timer 1 a match clock input. timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and t1 a match prescaler division rates (t2ck[2:0]). when the values of t2cnth/t2cntl and t2adrh/t2adrl are identical in timer 2, a match signal is generated and the interrupt of timer 2 occurs. the t2cnth/t2cntl values are automatically cleared by match signal. it can be also cleared by software (t2cc). t2ms[1:0] t2pol a match t2cc t2en p r e s c a l e r fx m u x fx/2 fx/4 fx/32 fx/128 fx/512 fx/8 fx/1 16 -bit counter t2cnth/t2cntl clear t1 a match comparator 16 -bit a data register t2adrh/t2adrl t2ifr int_ack clear to interrupt block a match buffer register a reload pulse generator t2 o r t2en 3 t2ck[2:0] 2 a match t2cc t2en t2 en t2crh 1 address:c3h initial value : 0000_0000 b C t2ms1 t2ms0 CC C t2c c C 00 CC C x t2ck2 t2 cr l x address:c2h initial value : 0000_0000 b t2 c k1 t 2c k0 t2i f r C t2pol C t2cntr xx x C x C x figure 11.22 16-bit timer/counter mode for timer 2
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 132 figure 11.23 16-bit timer/counter 2 example t2cnth/l v alue timer 2 (t2ifr) interrupt time 1 2 3 4 5 6 n-2 n-1 n interrupt period = p cp x (n+1) 0 count pulse period p cp up-count match with t2adrh/l occur interrupt occur interrupt occur interrupt
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 133 11.7.3 16-bit capture mode the timer 2 capture mode is set by t2ms[1:0] as ?01?. the clock source can use the internal clock. basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when t2cnth/t2cntl is equal to t2adrh/t2adrl. t2cnth/t2cntl values are automatically cleared by match signal and it can be also cleared by software (t2cc). this timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. the capture result is load ed into t2bdrh/t2bdrl. in the timer 2 capture mode, ti mer 2 output(t2o) waveform is not available. according to eipol1 registers setting, the external interrupt eint12 function is chosen. of cource, the eint12 pin must be set to an input port. a match t2cc t2en p r e s c a l e r fx m u x fx/2 fx/4 fx/32 fx/128 fx/512 fx/8 fx/1 16 -bit counter t2c n t h/ t 2c n t l 16 -bit b data register t2bdrh/t2bdrl clear t1 a match comparator 16 -bit a data register t2adrh/t2adrl t2ifr int_ack clear to interrupt block a match buffer register a reload r eint12 t2cntr t2en 3 t2ck[2:0] clear flag12 (eiflag1.3) int_ack clear to interrupt block t 2m s[1 :0] 2 a match t2cc t2en t2en t2crh 1 address:c3h initial value : 0000 _0000b C t2ms1 t2ms0 CCC t2cc C 01 CCC x t2 c k2 t2crl x address:c2h initial value : 0000 _0000b t2ck1 t2ck0 t2ifr C t2pol C t2cntr xx x C x C x eipol 1[7:6 ] 2 figure 11.24 16-bit capture mode for timer 2
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 134 figure 11.25 input capture mode operation for timer 2 figure 11.26 express timer overflow in capture mode t2cnth/l interrupt request (flag12) x x h interrupt interval period = ffff h +01 h +ffff h +01 h +yy h +01 h ext. eint12 pin interrupt request (t2ifr) ffff h ffff h yy h 00 h 00 h 00 h 00 h 00 h t2cnth/l v alue interrupt request (flag12) time 1 2 3 4 5 6 n-2 n-1 n interrupt interval period 0 count pulse period p cp up-count t2bdrh/l load ext. eint12 pin
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 135 11.7.4 16-bit ppg mode the timer 2 has a ppg (programmable pulse generation) function. in ppg mode, the t2o/pwm2o pin outputs up to 16-bit resolution pwm output. this pin should be configured as a pwm output by set p1fsrl[3:2] to ?11? . the peri od of the pwm output is dete rmined by the t2 adrh/t2adrl. and the duty of the pwm output is determined by the t2bdrh/t2bdrl. t2ms[1:0] t2pol reload a match t2cc t2en p r e s c a l e r fx m u x fx/2 fx/4 fx/32 fx/128 fx/512 fx/8 fx/1 comparator 16 -bit counter t2cnth/t2cntl 16-bit b data register t2bdrh/t2bdrl clear b match t1 a match buffer register b comparator 16 -bit a data register t2adrh/t2adrl t2 i f r int_ack clear to interrupt block a match buffer register a reload pulse generator t2o / pwm2 o r t2en 3 t 2c k[2 :0] 2 a match t2cc t2en a match t2cc t2en t2 en t2crh 1 address:c3h initial value : 0000_0000 b C t2ms1 t2ms0 CC C t2c c C 11 CC Cx t2ck2 t2 c r l x address:c2h initial value : 0000_0000 b t2 c k1 t 2c k0 t2i f r C t2pol C t2cntr xx x C x C x note) the t2en is automatically cleared to logic ?0? after one pulse is generated at a ppg one-shot mode. figure 11.27 16-bit ppg mode for timer 2
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 136 x124568m - 1m023 timer 2 clock counter t2adrh/l t2 interrupt pwm2o b match repeat mode(t2ms = 11b) and "start high"(t2pol = 0b). set t2en 0 clear and start 37 1 m a match 1. t2bdrh/l(5) < t2adrh/l pwm2o a match 2. t2bdrh/l >= t2adrh/l pwm2o a match 3. t2bdrh/l = "0000h" low level x124568m - 1m0 timer 2 clock counter t2adrh/l t2 interrupt pwm2o b match one-shot mode (t2ms = 10b) and "start high"(t2pol = 0b). set t2en 0 clear and start 37 m a match 1. t2bdrh/l(5) < t2adrh/l pwm2o a match 2. t2bdrh/l >= t2adrh/l pwm2o a match 3. t2bdrh/l = "0000h" low level figure 11.28 16-bit ppg mode timming chart for timer 2
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 137 11.7.5 block diagram t2ms[ 1:0] t 2pol reload a match t2cc t2en p r e s c a l e r fx m u x fx/2 fx/4 fx/32 fx/128 fx/512 fx/8 fx/1 comparator 16-bit counter t2cnth/t2cntl 16-bit b data register t2bdrh/t2bdrl clear b match buffer register b comparator 16-bit a data register t2adrh/t2adrl t2ifr int_ack clear to interrupt block a match buffer register a reload pulse generator t2o/ pwm2o r eint12 t2cntr t2en 3 t2ck[2:0] clear eipol 1[7:6 ] flag12 (eiflag1 .3) int_ack clear to interrupt block 2 2 t2ms[1:0] 2 t1 a m at c h a match t2cc t2en a match t2cc t2en figure 11.29 16-bit timer/counter mode for timer 2 and block diagram 11.7.6 register map table 11-10 timer 3 register map name address dir default description t2adrh c5h r/w ffh timer 2 a data high register t2adrl c4h r/w ffh timer 2 a data low register t2bdrh c7h r/w ffh timer 2 b data high register t2bdrl c6h r/w ffh timer 2 b data low register t2crh c3h r/w 00h timer 2 control high register t2crl c2h r/w 00h timer 2 control low register
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 138 11.7.6.1 timer/counter 2 register description the timer/counter 2 register consists of timer 2 a data high register (t2adrh), timer 2 a data low register (t2adrl), timer 2 b data high register (t2bdrh), timer 2 b data low register (t2bdrl), timer 2 control high register (t2crh) and timer 2 co ntrol low register (t2crl). 11.7.6.2 register description for timer/counter 2 t2adrh (timer 2 a data high register) : c5h 7 6 5 4 3 2 1 0 t2adrh7 t2adrh6 t2adrh5 t2adrh4 t2adrh3 t2adrh2 t2adrh1 t2adrh0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t2adrh[7:0] t2 a data high byte t2adrl (timer 2 a data low register) : c4h 7 6 5 4 3 2 1 0 t2adrl7 t2adrl6 t2adrl5 t2adrl4 t2adrl3 t2adrl2 t2adrl1 t2adrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t2adrl[7:0] t2 a data low byte note) do not write ?0000h? in the t2adrh/t2adrl register when ppg mode. t2bdrh (timer 2 b data high register) : c7h 7 6 5 4 3 2 1 0 t2bdrh7 t2bdrh6 t2bdrh5 t2bdrh4 t2bdrh3 t2bdrh2 t2bdrh1 t2bdrh0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t2bdrh[7:0] t2 b data high byte t2bdrl (timer 2 b data low register) : c6h 7 6 5 4 3 2 1 0 t2bdrl7 t2bdrl6 t2bdrl5 t2bdrl4 t2bdrl3 t2bdrl2 t2bdrl1 t2bdrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t2bdrl[7:0] t2 b data low
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 139 t2crh (timer 2 control high register) : c3h 7 6 5 4 3 2 1 0 t2en ? t2ms1 t2ms0 ? ? ? t2cc r/w ? r/w r/w ? ? ? r/w initial value : 00h t2en control timer 2 0 timer 2 disable 1 timer 2 enable (counter clear and start) t2ms[1:0] control timer 2 operation mode t2ms1 t2ms0 description 0 0 timer/counter mode (t2o: toggle at a match) 0 1 capture mode (the a match interrupt can occur) 1 0 ppg one-shot mode (pwm2o) 1 1 ppg repeat mode (pwm2o) t2cc clear timer 2 counter 0 no effect 1 clear the timer 2 counter (when write, automatically cleared ?0? after being cleared counter)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 140 t2crl (timer 2 control low register) : cah 7 6 5 4 3 2 1 0 t2ck2 t2ck1 t2ck0 t2ifr ? t2pol ? t2cntr r/w r/w r/w r/w ? r/w ? r/w initial value : 00h t2ck[2:0] select timer 2 clock source. fx is main system clock frequency t2ck2 t2ck1 t2ck0 description 0 0 0 fx/512 0 0 1 fx/128 0 1 0 fx/32 0 1 1 fx/8 1 0 0 fx/4 1 0 1 fx/2 1 1 0 fx/1 1 1 1 t1 a match t2ifr when t2 match interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or auto clear by int_ack signal. 0 t2 interrupt no generation 1 t2 interrupt generation t2pol t2o/pwm2o polarity selection 0 start high (t2o/pwm2o is low level at disable) 1 start low (t2o/pwm2o is high level at disable) t2cntr timer 2 counter read control 0 no effect 1 load the counter value to the b data register (when write, automatically cleared ?0? after being loaded)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 141 11.8 timer 3, 4 11.8.1 overview timer 3 and timer 4 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. each 8-bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register (t3cnt, t3dr, t3capr, t3cr, t4cnt, t4dr, t4capr, t4cr). for pwm, it has pwm register (t4pprl. t4pprh, t4 adrl, t4adrh, t4bdrl, t4bdrh, t4cdrl, t4cdrh, t4dlya, t4dlyb, t4dlyc). it has five operating modes: - 8-bit timer/counter mode - 8-bit capture mode - 16-bit timer/counter mode - 16-bit capture mode - 10-bit pwm mode the timer/counter 3 and 4 can be clocked by an internal or an external clock source (ec3). the clock source is selected by clock selection logic which is controlled by the clock selection bits (t3ck[2:0], t4ck[3:0]). also the timer/counter 4 can use more clock sources than timer/counter 3. - timer 3 clock source: f x /2, 4, 8, 32, 128, 512, 2048 and ec3 - timer 4 clock source: f x /1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 and t3 clock in the capture mode, by eint0/eint1, the data is captured into input capture data register (t3capr, t4capr). in 8-bit timer/counter 3/4 mode, whenever counter value is equal to t3dr/t4dr, t3o/t4o port toggles. also in 16-bit timer/counter 3 mode, the timer 3 outputs the comparison result between counter and data register through t3o port. the pwm wave form to pwmaa, pwmab, pwmba, pwmbb, pwmca, pwmcb port (6-channel) in the pwm mode. table 11-11 timer 3, 4 operating modes 16bit t3ms t4ms pwm4e t3ck[2:0] t4ck[3:0] timer 3 timer 4 0 0 0 0 xxx xxxx 8 bit timer/counter mode 8 bit timer/counter mode 0 1 1 0 xxx xxxx 8 bit capture mode 8 bit capture mode 1 0 0 0 xxx xxxx 16 bit tmer/counter mode 1 1 1 0 xxx xxxx 16 bit capture mode 0 x x 1 xxx xxxx 10 bit pwm mode
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 142 11.8.2 8-bit timer/counter 3, 4 mode the 8-bit timer/counter mode is selected by control register as shown in figure 11.30. the two 8-bit timers have each counter and data register. the counter register is increased by internal or external clock input. timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and ec3 prescaler division rates (t3ck[2:0]). timer 4 can use the input clock with one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 and timer 3 clock prescaler division rates (t4ck[3:0]). when the value of t3cnt, t4cnt and t3dr, t4dr are respectively identical in timer 3, 4, the interrupt timer 3, 4 occurs. the external clock (ec3) counts up the timer at the rising edge. if the ec3 is selected as a clock source by t3ck[2:0], ec3 port should be set to the input port by p00io bit. timer 4 can?t use the external ec3 clock. t3en t3cr 1 address:1000h (esfr) initial value : 0000 _0000 b C t3ms t3ck2 t3ck1 t3ck0 t3cn t3st C 0x xx x x 16bit t4cr 0 address:1002h (esfr) initial value : 0000 _0000 b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 0x xxx x x p r e s c a l e r fx m u x fx/2 t3cnt (8bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 8-bit timer 3 counter t3dr (8bit) comparator t3ifr to interrupt block t3 o 8-bit timer 3 data register int_ack clear clear match t3st t4cnt (8bit) 4 t4ck[3:0] 8-bit timer 4 counter t4dr (8bit) comparator to interrupt block t4o 8-bit timer 4 data register clear match t4st p r e s c a l e r fx m u x fx/1 fx/2 fx/4 fx/8 fx/16384 t4 c n note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.30 8-bit timer/counter mode for timer 3, 4
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 143 11.8.3 16-bit timer/counter 3 mode the 16-bit timer/counter mode is selected by control register as shown in figure 11.31. the 16-bit timer have counter and data register. the counter register is increased by internal or external clock input. timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (t3ck[2:0]). a 16-bit timer/counter register t3cnt, t4cnt are incremented from 0000h to ffffh until it matches t3dr, t4dr and then cleared to 0000h. the match signal output generates the timer 3 interrupt (no timer 4 interrupt). the clock source is selected from t3ck[2:0] and 16bit bit must be set to ?1?. timer 3 is lsb 8-bit, the timer 4 is msb 8-bit. the external clock (ec3) counts up the timer at the rising edge. f the ec3 is selected as a clock source by t3ck[2:0], ec3 port should be set to the input port by p00io bit. p r e s c a l e r fx m u x fx/2 t4cnt/t3cnt (16bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 16-bit timer 3 counter t4dr/t3dr (16bit) comparator t3ifr to interrupt block t3 o 16-bit timer 3 data register int_ack clear clear match t3st msb lsb msb lsb t3en t3 cr 1 address:1000 h (esfr) initial value : 0000 _0000b C t3ms t3ck2 t3ck1 t3ck0 t3cn t3st C 0x xxx x 16bit t4 cr 1 address:1002 h (esfr) initial value : 0000 _0000b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 0x x11 1 1 note) the t4cr.7 bit (16bit) should be set to ?1? and the t4ck[3:0] should be set to ?1111b?. figure 11.31 16-bit timer/counter mode for timer 3
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 144 11.8.4 8-bit timer 3, 4 capture mode the 8-bit capture 3 and 4 mode is selected by control register as shown in figure 11.32. the timer 3, 4 capture mode is set by t3ms, t4ms as ?1?. the clock source can use the internal/external clock. basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when t3cnt, t4cnt is equal to t3dr, t4dr. the t3cnt, t4cnt value is automatically cleared by match signal. this timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. the capture result is loaded into t3capr, t4capr. in the timer 3, 4 capture mode, timer 3, 4 output (t3o, t4o) waveform is not available. according to the eipol0l register setting, the external interrupt eint0 and eint1 function is chose. of cource, the eint0 and eint1 pins must be set to an input port. the t3capr and t3dr are in the same address. in the capture mode, reading operation reads t3capr, not t3dr and writing operation will update t3dr. the t4capr has the same function.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 145 p r e s c a l e r fx m u x fx/2 t3cnt (8bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 8-bit timer 3 counter t3dr (8bit) comparator t3ifr to interrupt block t3 o 8-bit timer 3 data register int_ack clear clear match t3capr (8bit) clear eint0 eipol 0l[1:0 ] flag0 (eiflag0.0) s/w clear to interrupt block 2 t3ms t3st 8-bit timer 3 capture register t4cnt (8bit) 4 t4ck[3:0] 8-bit timer 4 counter t4dr (8bit) comparator to interrupt block t4o 8-bit timer 4 data register clear match t4capr (8bit) clear eint1 eipol 0l[3:2 ] flag0 (eiflag0.1) s/w clear to interrupt block 2 t4st 8-bit timer 4 capture register p r e s c a l e r fx m u x fx/1 fx/2 fx/4 fx/8 fx/16384 t4ms t4 c n t3en t3cr 1 address:1000h (esfr) initial value : 0000 _0000 b C t3ms t3ck2 t3ck1 t3 ck0 t3cn t3st C 1x xxx x 16bit t4cr 0 address:1002h (esfr) initial value : 0000 _0000 b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 1x xxx x x note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.32 8-bit capture mode for timer 3, 4
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 146 11.8.5 16-bit timer 3 capture mode the 16-bit capture mode is selected by control register as shown in figure 11.33. the 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. the 16-bit timer 3 capture mode is set by t3ms, t4ms as ?1? . the clock source is selected from t3ck[2:0] and 16bit bit must be set to ?1?. timer 3 is lsb 8-bit, the timer 4 is msb 8-bit. p r e s c a l e r fx m u x fx/2 t4cnt/t3cnt (16bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 16-bit timer 3 counter t4dr/t3dr (16bit) comparator t3ifr to interrupt block t3 o 16-bit timer 3 data register int_ack clear clear match t4capr/t3capr (16 bit) clear eint0 eipol 0l[1:0 ] flag 0 (eiflag0.0) s/w clear to interrupt block 2 t3ms t3st 16-bit timer 3 capture register msb lsb msb lsb msb lsb t3en t3 cr 1 address:1000 h (esfr) initial value : 0000 _0000b C t3ms t3ck2 t3ck1 t3ck0 t3cn t3st C 1x xxx x 16bit t4 cr 1 address:1002 h (esfr) initial value : 0000 _0000b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 1x x11 1 1 note) the t4cr.7 bit (16bit) should be set to ?1? and the t4ck[3:0] should be set to ?1111b?. figure 11.33 16-bit capture mode for timer 3
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 147 11.8.6 10-bit timer 4 pwm mode the timer 4 has a high speed pwm (pulse width modulation) function. in pwm mode, the 6-channel pins output up to 10-bit resolution pwm output. this pin should be configured as a pwm output by set pwm4e to ?1?. when the value of 2bit +t4cnt and t4pprh/l are identical in timer 4, a period match sign al is generated and the interrupt of timer 4 occurs. in 10-bit pwm mode, a, b, c, bottom(underflow) match signal are generated when the 10-bit counter value are identical to the value of t4xadrh/l. the period of the pwm output is determined by the t4pprh/l (pwm period register), t4xdrh/l (each channel pwm duty register). pwm period = [t4pprh/t4pprl ] x source clock pwm duty(a-ch) = [ t4adrh/t4adrl ] x source clock table 11-12 pwm frequency vs. resolution at 8 mhz resolution frequency t4ck[3:0]=0001 (250ns) t4ck[3:0]=0010 (500ns) t4ck[3:0]=0100 (2us) 10 bit 3.9khz 1.95khz 0.49khz 9 bit 7.8khz 3.9khz 0.98khz 8 bit 15.6khz 7.8khz 1.95khz 7 bit 31.2khz 15.6khz 3.91khz the polxa bit of t4pcr3 register decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit polxa (1: high, 0: low). and if the duty value is set to "00h", the pwm output is determined by the bit polxa (1: low, 0: high). table 11-13 pwm channel polarity phlt:pxxoe polxa polbo polxb pwm4xa pin output pwm4xb pin output 0x, x0, 00 0 0 0 low-level low-level 1 low-level high-level 1 x low-level low-level 1 0 0 high-level high-level 1 high-level low-level 1 x high-level high-level 11 0 x 0 positive-phase positive-phase 1 positive-phase negative-phase 1 x 0 negative-phase negative-phase 1 negative-phase positive-phase
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 148 p r e s c a l e r fx m u x fx/2 fx/4 fx/16 fx/32 fx/64 fx/8 fx/1 comparator 10 -bit counter 2bit + t4cnt 10-bit a data register t4adrh/t4adrl control up/down comparator t4pprh/t4pprl (10 bit) period match pwm output control a-ch pwm4aa t4cn 4 t4ck[3:0] fx/128 fx/256 fx/1024 fx/2048 fx/4096 fx/512 fx/8192 fx/16384 timer 4 pwm period register t4 st pwm delay control a-ch pwm4ab comparator 10-bit b data register t4bdrh/t4bdrl pwm output control b-ch pwm4 ba pwm delay control b-ch pwm4 bb comparator 10-bit c data register t4cdrh/t4cdrl pwm output control c-ch pwm4 ca pwm delay control c-ch pwm4 cb a match b match c match interrupt generator a match b match c match bottom (underflow) to interrupt block forca t4pcr2 0 address:1004h ( esfr) initial value : 0000 _0000 b C paaoe paboe pbaoe pbboe pcaoe pcboe C xx xx x x hzclr t4pcr3 x address:1005h ( esfr) initial value : 0000 _0000 b polbo polaa polab polba polbb polca polcb xx xxx x x 16bit t4cr 0 address:1002h ( esfr) initial value : 0000 _0000 b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 xxx xx x x pwm4e t4pcr1 1 address:1003h ( esfr) initial value : 0000 _0000 b esync bmod phlt updt uall nops1 nops0 xx xxx x x note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.34 10-bit pwm mode (force 6-ch)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 149 p r e s c a l e r fx m u x fx/2 fx/4 fx/16 fx/32 fx/64 fx/8 fx/1 comparator 10 -bit counter 2bit + t4cnt 10-bit a data register t4adrh/t4adrl control up/down comparator t4pprh/t4pprl (10 bit) period match pwm output control a-ch pwm4aa t4cn 4 t4ck[3:0] fx/128 fx/256 fx/1024 fx/2048 fx/4096 fx/512 fx/8192 fx/16384 timer 4 pwm period register t4 st pwm delay control a-ch pwm4ab pwm output control b-ch pwm4 ba pwm delay control b-ch pwm4 bb pwm output control c-ch pwm4 ca pwm delay control c-ch pwm4 cb a match interrupt generator a match b match c match bottom (underflow) to interrupt block forca t4pcr2 1 address:1004h ( esfr) initial value : 0000 _0000 b C paaoe paboe pbaoe pbboe pcaoe pcboe C xx xx x x hzclr t4pcr3 x address:1005h ( esfr) initial value : 0000 _0000 b polbo polaa polab polba polbb polca polcb xx xxx x x 16bit t4cr 0 address:1002h ( esfr) initial value : 0000 _0000 b t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 xxx xx x x pwm4e t4pcr1 1 address:1003h ( esfr) initial value : 0000 _0000 b esync bmod phlt updt uall nops1 nops0 xx xxx x x note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.35 10-bit pwm mode (force all-ch)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 150 figure 11.36 example of pwm at 4 mhz figure 11.37 example of changing the period in absolute duty cycle at 4 mhz update period & duty register value at once the period and duty of pwm comes to move from temporary registers to t4pprh/l (pwm period register) and t4adrh/l/t4bdrh/l/t4cdrh/l (pwm duty register) when always period match occu rs. if you want that the period and duty is immediately changed, the updt bit in the t4pcr1 register must set to ?1?. it should be noted that it needs the 3 cycle of timer clock for data transfer in the internal clock synchronization circuit. so the update data is written before 3 cycle of timer clock to get the right output waveform. t4cnt 00 01 02 03 04 p02/pwm4aa polaa = 1 t4cr = 03 h (2us) t4pprh = 00 h t4pprl = 0e h t4adrh = 00 h t4adrl = 05 h 09 08 0706 05 0d 0c 0b 0a 02 01 00 0e 06 050403 0a 090807 03 02 01 00 05 04 source clock (f x ) 06 duty cycle ( 1+05 h ) x2us = 12us duty cycle ( 1+05 h ) x2us = 12us duty cycle ( 1+05 h ) x2us = 12us period cycle (1+0e h )x2us = 32us ? 31.25khz period cycle (1+0a h )x2us = 22us ? 45.5khz write 0a h to t4pprl source clock (f x ) duty cycle(1+80 h )x250ns = 32.25us t4cnt 00 01 02 03 04 7f 80 81 82 3ff 00 01 02 p02/pwm4aa polaa = 1 p02/pwm4aa polaa = 0 period cycle(1+3ff h )x250ns = 256us ? 3.9khz t4pprl(8 bit) t4adrl(8 bit) t4pprh(2 bit) t4adrh(2 bit) 03 h ff h 00 h 80 h t4cr = 00 h (f xin ) t4pprh = 03 h t4pprl = ff h t4adrh = 00 h t4adrl = 80 h
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 151 phase correction & fr equency correction on operating pwm, it is possible that it is changed the phase and the frequency by using bmod bit (back-to- back mode) in t4pcr1 register. (figure 1.38, figure 11.39, figure 11.40 referred) in the back-to-back mode, the counter of pwm repeats up/down count. in fact, the effective duty and period becomes twofold of the register set values. (figure 1.38, figure 11.39 referred) figure 11.38 example of pwm output waveform figure 11.39 example of pwm waveform in back-to-back mode at 4 mhz t4cnt 00 01 02 03 04 p02/pwm4aa polaa = 1 t4cr = 03 h (2us) t4pprh = 00 h t4pprl = 0b h t4adrh = 00 h t4adrl = 05 h 09 08 0706 05 0 a 0b 0b 0a 06 070809 02 030405 01 00 00 01 05 04 03 02 07 06 source clock (f x ) 08 duty cycle ( 1+05 h ) x2us = 12us duty cycle ( 1+05 h ) x2us = 12us duty cycle ( 1+05 h ) x2us = 12us period cycle (1+0b h )x2us = 26us ? 38.46khz start down counter period cycle (1+0b h )x2us = 26us ? 38.46khz duty match detect start up counter duty match detect t4cnt duty normal pwm mode 00 h 00 h 00 h 00 h 00 h max max max max period duty, period update t4cnt duty back-to-back mode 00 h 00 h 00 h max max max period duty, period update duty period non back-to-back mode back-to-back mode
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 152 figure 11.40 example of phase correction and frequency correction of pwm external sync if using esync bit of t4pcr1 register, it is possible to synchronize the output of pwm from external signal. if esync bit sets to ?1?, the external signal moves to pwm module through the blnk pin. if blnk signal is low, immediately pwm output becomes a reset value, and internal counter becomes reset. if blnk signal returns to ?1?, the counter is started again and pwm output is normally generated. (figure 11.41 referred) pwm halt if using phlt bit of t4pcr1 register, it is possible to stop pwm operation by the software. during phlt bit being ?1?, pwm output becomes a reset value, and internal counter becomes reset as 0. without changing pwm setting, temporarily it is able to stop pwm. in case of t4cnt, when stopping counter, pwm output pin remains before states. but if phlt bit sets to ?1?, pwm output pin has reset value. figure 11.41 example of pwm external synchronization with blnk input t4 00 01 02 12 t4pcr1 = 40 h (eync=1) t4pprh = 00 h t4pprl = 2a h t4adrh = 00 h t4adrl = 12 h 00 14 13 0201 00 141312 00 0000 03 02 01 14 13 12 00 2a source clock (f x ) 01 blnk ?0? pwm stop blnk ?1? pwm restart 2a 02 p02/pwm polaa = 1 blnk esync = 1 counter stop t4cnt duty1 back-to-back mode 00 h 00 h 00 h max max max period1 duty, period update duty2 period2 duty3 period3 overflow int. overflow int. bottom int. overflow int. interrupt timing
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 153 force drive all channel with a-ch mode if forca bit sets to ?1?, it is possible to enable or disable all pwm output pins through pwm outputs which occur from a-ch duty counter. it is noted that the inversion outputs of a, b, c channel have the same a-ch output waveform. according to polaa/bb/cc, it is able to control the inversion of outputs. figure 11.42 example of force drive all channel with a-ch pwma paaoe pwm4aa paboe pwm4ab pbaoe pwm4ba pbboe pwm4bb forca - paaoe paboe pbaoe pbboe pcaoe pcboe t4pcr2 1 - x x x x x x address : 1004h (esfr) initial value : 0-00_0000b c-ch operation is the same with channel a and b waveform
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 154 force 6-ch drive if forca bit sets to ?0?, it is possible to enable or disable pwm output pin and inversion output pin generated through the duty counter of each channel. the inversion output is the reverse phase of the pwm output. a aa/ab output of the a-channel duty register, a ba/bb output of the b-channel duty register, a ca/cb output of the c- channel duty register are controlled respectively. if the uall bit is set to ?1?, it is updated b/c channel duty at the same time, when it is written by a a-channel duty register. figure 11.43 example of force drive 6-ch mode pwma paaoe pwm4aa paboe pwm4ab pbaoe pwm4ba pbboe pwm4bb forca - paaoe paboe pbaoe pbboe pcaoe pcboe t4pcr2 0 - x x x x x x address : 1004h (esfr) initial value : 0-00_0000b c-ch operation is the same with channel a and b waveform pwmb
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 155 pwm output delay if using the t4dlya, t4dlyb, t4dlyc register, it can delay pwm output based on the rising edge. at that time, it does not change the falling edge, so the duty is reduced as the time delay. in polaa/ba/ca setting to ?0?, the delay is applied to the falling edge. in polaa/ba/ca setting to ?1?, the delay is applied to the rising edge. it can produce a pair of non-overlapping clock. the each channel is able to have 4-bit delay. as it can select the clock up to 1/8 divided clock using nops[1:0] the delay of its maximum 128 timer clock cycle is produced.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 156 pwma pwm4aa pwm4ab pwma pwm4aa pwm4ab t4dlyaa = 02 h t4dlyab = 04 h b-ch and c-ch operation is the same with channel a waveform pwma pwm4ab pwm4aa t4dlyaa = 02 h t4dlyab = 04 h forca - paaoe paboe pbaoe pbboe pcaoe pcboe t4pcr2 0 - x x x x x x hzclr polbo polaa polab polba polbb polca t4pcr3 x x 1 1 x x x x t4dlyaa3 t4dlyaa2 t4dlyaa1 t4dlyaa0 t4dlyab 3 t4dlyab 2 t4dlyab 1 t4dlyab 0 t4dlya 0 0 0 0 0 0 0 0 polcb address : 1004h (esfr) initial value : 0-00_0000b address : 1005h (esfr) initial value : 0000_0000b address : 1010h (esfr) initial value : 0000_0000b forca - paaoe paboe pbaoe pbboe pcaoe pcboe t4pcr2 0 - x x x x x x hzclr polbo polaa polab polba polbb polca t4pcr3 x x 1 1 x x x x t4dlyaa3 t4dlyaa2 t4dlyaa1 t4dlyaa0 t4dlyab 3 t4dlyab 2 t4dlyab 1 t4dlyab 0 t4dlya 0 0 1 0 0 1 0 0 polcb address : 1004h (esfr) initial value : 0-00_0000b address : 1005h (esfr) initial value : 0000_0000b address : 1010h (esfr) initial value : 0000_0000b forca - paaoe paboe pbaoe pbboe pcaoe pcboe t4pcr2 0 - x x x x x x hzclr polbo polaa polab polba polbb polca t4pcr3 x x 0 1 x x x x t4dlyaa3 t4dlyaa2 t4dlyaa1 t4dlyaa0 t4dlyab 3 t4dlyab 2 t4dlyab 1 t4dlyab 0 t4dlya 0 0 1 0 0 1 0 0 polcb address : 1004h (esfr) initial value : 0-00_0000b address : 1005h (esfr) initial value : 0000_0000b address : 1010h (esfr) initial value : 0000_0000b
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 157 figure 11.44 example of pwm delay 11.8.7 block diagram p r e s c a l e r fx m u x fx/2 t3cnt (8bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 8-bit timer 3 counter t3dr (8bit) comparator t3ifr to interrupt block t3 o 8-bit timer 3 data register int_ack clear clear match t3capr (8bit) clear eint0 eipol 0l[1:0 ] flag0 (eiflag0.0) int_ack clear to interrupt block 2 t3ms t3st 8-bit timer 3 capture register t4cnt (8bit) 4 t4ck[3:0] 8-bit timer 4 counter t4dr (8bit) comparator to interrupt block t4o 8-bit timer 4 data register clear match t4capr (8bit) clear eint1 eipol 0l[3:2 ] flag0 (eiflag0.1) int_ack clear to interrupt block 2 t4st 8-bit timer 4 capture register p r e s c a l e r fx m u x fx/1 fx/2 fx/4 fx/8 fx/16384 t4ms t4 c n note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.45 two 8-bit timer 3, 4 block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 158 p r e s c a l e r fx m u x fx/2 t4cnt/t3cnt (16bit) ec3 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048 3 t3ck[2:0] t3c n 16-bit timer 3 counter t4dr/t3dr (16bit) comparator t3ifr to interrupt block t3 o 16-bit timer 3 data register int_ack clear clear match t4capr/t3capr (16 bit) clear eint0 eipol 0l[1:0 ] flag0 (eiflag0.0) int_ack clear to interrupt block 2 t3ms t3st 16-bit timer 3 capture register msb lsb msb lsb msb lsb note) the t4cr.7 bit (16bit) should be set to ?1? and the t4ck[3:0] should be set to ?1111b?. figure 11.46 16-bit timer 3 block diagram p r e s c a l e r fx m u x fx/2 fx/4 fx/16 fx/32 fx/64 fx/8 fx/1 comparator 10 -bit counter 2bit + t4cnt 10-bit a data register t4adrh/t4adrl control up/down comparator t4pprh/t4pprl (10 bit) period match pwm output control a-ch pwm4aa t4cn 4 t4ck[3:0] fx/128 fx/256 fx/1024 fx/2048 fx/4096 fx/512 fx/8192 fx/16384 timer 4 pwm period register t4 st pwm delay control a-ch pwm4ab comparator 10-bit b data register t4bdrh/t4bdrl pwm output control b-ch pwm4 ba pwm delay control b-ch pwm4 bb comparator 10-bit c data register t4cdrh/t4cdrl pwm output control c-ch pwm4 ca pwm delay control c-ch pwm4 cb a match b match c match interrupt generator a match b match c match bottom (underflow) to interrupt block note: do not set to ?1111b? in the t4ck[3:0], when two 8-bit timer 3/4 modes. figure 11.47 10-bit pwm timer 4 block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 159 11.8.8 register map table 11-14 timer 3, 4 register map name address dir default description t3cnt 1001h (esfr) r 00h timer 3 counter register t3dr 1001h (esfr) w ffh timer 3 data register t3capr 1001h (esfr) r 00h timer 3 capture data register t3cr 1000h (esfr) r/w 00h timer 3 control register t4pprh 1009h (esfr) r/w 00h timer 4 pwm period high register t4pprl 1008h (esfr) r/w ffh timer 4 pwm period low register t4adrh 100bh (esfr) r/w 00h timer 4 pwm a duty high register t4adrl 100ah (esfr) r/w 7fh timer 4 pwm a duty low register t4bdrh 100dh (esfr) r/w 00h timer 4 pwm b duty high register t4bdrl 100ch (esfr) r/w 7fh time r 4 pwm b duty low register t4cdrh 100fh (esfr) r/w 00h timer 4 pwm c duty high register t4cdrl 100eh (esfr) r/w 7fh timer 4 pwm c duty low register t4dlya 1010h (esfr) r/w 00h timer 4 pwm a delay register t4dlyb 1011h (esfr) r/w 00h timer 4 pwm b delay register t4dlyc 1012h (esfr) r/w 00h timer 4 pwm c delay register t4dr 1013h (esfr) r/w ffh timer 4 data register t4capr 1014h (esfr) r 00h timer 4 capture data register t4cnt 1015h (esfr) r 00h timer 4 counter register t4cr 1002h (esfr) r/w 00h timer 4 control register t4pcr1 1003h (esfr) r/w 00h ti mer 4 pwm control register 1 t4pcr2 1004h (esfr) r/w 00h ti mer 4 pwm control register 2 t4pcr3 1005h (esfr) r/w 00h ti mer 4 pwm control register 3 t4isr 1006h (esfr) r/w 00h timer 4 interrupt status register t4msk 1007h (esfr) r/w 00h timer 4 interrupt mask register
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 160 11.8.8.1 timer/counter 3 register description the timer/counter 3 register consists of timer 3 counter register (t3cnt), timer 3 data register (t3dr), timer 3 capture data register (t3capr) and timer 3 control register (t3cr). 11.8.8.2 register description for timer/counter 3 t3cnt (timer 3 counter register: read case, timer mode only) : 1001h (esfr) 7 6 5 4 3 2 1 0 t3cnt7 t3cnt6 t3cnt5 t3cnt4 t3cnt3 t3cnt2 t3cnt1 t3cnt0 r r r r r r r r initial value : 00h t3cnt[7:0] t3 counter t3dr (timer 3 data register : write case) : 1001h (esfr) 7 6 5 4 3 2 1 0 t3dr7 t3dr6 t3dr5 t3dr4 t3dr3 t3dr2 t3dr1 t3dr0 w w w w w w w w initial value : ffh t3dr[7:0] t3 data t3capr (timer 3 capture data register: read case, capture mode only) : 1001h (esfr) 7 6 5 4 3 2 1 0 t3capr7 t3capr 6 t3capr 5 t3capr 4 t3capr 3 t3capr 2 t3capr 1 t3capr 0 r r r r r r r r initial value : 00h t3capr[7:0] t3 capture data
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 161 t3cr (timer 3 control register) : 1000h (esfr) 7 6 5 4 3 2 1 0 t3en ? t3ms t3ck2 t3ck1 t3ck0 t3cn t3st r/w ? r/w r/w r/w r/w r/w r/w initial value : 00h t3en control timer 3 0 timer 3 disable 1 timer 3 enable t3ms control timer 3 operation mode 0 timer/counter mode (t3o: toggle at match) 1 capture mode (the match interrupt can occur) t3ck[2:0] select timer 3 clock source. fx is main system clock frequency t3ck2 t3ck1 t3ck0 description 0 0 0 fx/2 0 0 1 fx/4 0 1 0 fx/8 0 1 1 fx/32 1 0 0 fx/128 1 0 1 fx/512 1 1 0 fx/2048 1 1 1 external clock (ec3) t3cn control timer 3 count pause/continue 0 temporary count stop 1 continue count t3st control timer 3 start/stop 0 counter stop 1 clear counter and start note) refer to the external interrupt flag 1 register (eiflag1) tor the t3 interrupt flag.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 162 11.8.8.3 timer/counter 4 register description the timer/counter 4 register consists of timer 4 pwm period high/low register (t4pprh/l), timer 4 pwm a duty high/low register (t4adrh/l), timer 4 pwm b duty high/low register (t4bdrh/l), ), timer 4 pwm c duty high/low register (t4cdrh/l), timer 4 pwm a delay register (t4dlya), timer 4 pwm b delay register (t4dlyb), timer 4 pwm c delay register (t4dlyc), timer 4 data register (t4dr), timer 4 capture data register (t4capr), timer 4 counter register (t4cnt), timer 4 control register (t4cr), timer 4 pwm control register 1 (t4pcr1), timer 4 pwm control register 2 (t4pcr2), timer 4 pwm control register 3 (t4pcr3), timer 4 interrupt status register (t4isr) and timer 4 interrupt mask register (t4msk). 11.8.8.4 register description for timer/counter 4 t4pprh (timer 4 pwm period high register : 6-ch pwm mode only) : 1009h (esfr) 7 6 5 4 3 2 1 0 ? ? ? ? ? ? t4pprh1 t4pprh0 ? ? ? ? ? ? r/w r/w initial value : 00h t4pprl[1:0] t4 pwm period data high byte t4pprl (timer 4 pwm period low register : 6-ch pwm mode only) : 1008h (esfr) 7 6 5 4 3 2 1 0 t4pprl7 t4pprl6 t4pprl5 t4pprl4 t4pprl3 t4pprl2 t4pprl1 t4pprl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t4pprl[7:0] t4 pwm period data low byte t4adrh (timer 4 pwm a duty high register : 6-ch pwm mode only) : 100bh (esfr) 7 6 5 4 3 2 1 0 ? ? ? ? ? ? t4adrh1 t4adrh0 ? ? ? ? ? ? r/w r/w initial value : 00h t4adrl[1:0] t4 pwm a duty data high byte t4adrl (timer 4 pwm a duty low register : 6-ch pwm mode only) : 100ah (esfr) 7 6 5 4 3 2 1 0 t4adrl7 t4adrl6 t4adrl5 t4adrl4 t4adrl3 t4adrl2 t4adrl1 t4adrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 7fh t4adrl[7:0] t4 pwm a duty data low byte
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 163 t4bdrh (timer 4 pwm b duty high register : 6-ch pwm mode only) : 100dh (esfr) 7 6 5 4 3 2 1 0 ? ? ? ? ? ? t4bdrh1 t4bdrh0 ? ? ? ? ? ? r/w r/w initial value : 00h t4bdrl[1:0] t4 pwm b duty data high byte t4bdrl (timer 4 pwm b duty low register : 6-ch pwm mode only) : 100ch (esfr) 7 6 5 4 3 2 1 0 t4bdrl7 t4bdrl6 t4bdrl5 t4bdrl4 t4bdrl3 t4bdrl2 t4bdrl1 t4bdrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 7fh t4bdrl[7:0] t4 pwm b duty data low byte t4cdrh (timer 4 pwm c duty high register : 6-ch pwm mode only) : 100fh (esfr) 7 6 5 4 3 2 1 0 ? ? ? ? ? ? t4cdrh1 t4cdrh0 ? ? ? ? ? ? r/w r/w initial value : 00h t4cdrl[1:0] t4 pwm c duty data high byte t4cdrl (timer 4 pwm c duty low register : 6-ch pwm mode only) : 100eh (esfr) 7 6 5 4 3 2 1 0 t4cdrl7 t4cdrl6 t4cdrl5 t4cdrl4 t4cdrl3 t4cdrl2 t4cdrl1 t4cdrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 7fh t4cdrl[7:0] t4 pwm c duty data low byte t4dlya (timer 4 pwm a delay register : 6-ch pwm mode only) : 1010h (esfr) 7 6 5 4 3 2 1 0 t4dlyaa3 t4dlyaa2 t4dlyaa1 t4dlyaa0 t4dlyab3 t4dlyab2 t4dlyab1 t4dlyab0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h t4dlyaa[3:0] pwm4aa delay data (rising edge only) t4dlyab[3:0] pwm4ab delay data (rising edge only) t4dlyb (timer 4 pwm b delay register : 6-ch pwm mode only) : 1011h (esfr) 7 6 5 4 3 2 1 0 t4dlyba3 t4dlyba2 t4dlyba1 t4dlyba0 t4dlybb3 t4dlybb2 t4dlybb1 t4dlybb0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h t4dlyba[3:0] pwm4ba delay data (rising edge only) t4dlybb[3:0] pwm4bb delay data (rising edge only)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 164 t4dlyc (timer 4 pwm c delay register : 6-ch pwm mode only) : 1012h (esfr) 7 6 5 4 3 2 1 0 t4dlyca3 t4dlyca2 t4dlyca1 t4dlyca0 t4dlycb3 t4dlycb2 t4dlycb1 t4dlycb0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h t4dlyca[3:0] pwm4ca delay data (rising edge only) t4dlycb[3:0] pwm4cb delay data (rising edge only) t4dr (timer 4 data register: timer and capture mode only) : 1013h (esfr) 7 6 5 4 3 2 1 0 t4dr7 t4dr6 t4dr5 t4dr4 t4dr3 t4dr2 t4dr1 t4dr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh t4dr[7:0] t4 data t4capr (timer 4 capture data register: read case, capture mode only) : 1014h (esfr) 7 6 5 4 3 2 1 0 t4capr7 t4capr6 t4capr5 t4capr4 t4capr3 t4capr2 t4capr1 t4capr0 r r r r r r r r initial value : 00h t4capr[7:0] t4 capture data t4cnt (timer 4 counter register: read case, timer mode only) : 1015h (esfr) 7 6 5 4 3 2 1 0 t4cnt7 t4cnt6 t4cnt5 t4cnt4 t4cnt3 t4cnt2 t4cnt1 t4cnt0 r r r r r r r r initial value : 00h t4cnt[7:0] t4 counter
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 165 t4cr (timer 4 control register) : 1002h (esfr) 7 6 5 4 3 2 1 0 16bit t4ms t4cn t4st t4ck3 t4ck2 t4ck1 t4ck0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h 16bit select two 8-bit or 16-bit mode for timer 3/4 0 two 8-bit timer 3/4 1 16-bit timer 3 t4ms control timer 4 operation mode 0 timer/counter mode (t4o: toggle at match) 1 capture mode (the match interrupt can occur) t4cn control timer 4 count pause/continue 0 temporary count stop 1 continue count t4st control timer 4 start/stop 0 counter stop 1 clear counter and start t4ck[3:0] select timer 4 clock source. fx is main system clock frequency t4ck3 t4ck2 t4ck1 t4ck0 description 0 0 0 0 fx/1 0 0 0 1 fx/2 0 0 1 0 fx/3 0 0 1 1 fx/8 0 1 0 0 fx/16 0 1 0 1 fx/32 0 1 1 0 fx/64 0 1 1 1 fx/128 1 0 0 0 fx/256 1 0 0 1 fx/512 1 0 1 0 fx/1024 1 0 1 1 fx/2048 1 1 0 0 fx/406 1 1 0 1 fx/8192 1 1 1 0 fx/16384 1 1 1 1 timer 3 clock (only 16-bit timer 3)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 166 t4pcr1 (timer 4 pwm control register 1) : 1003h (esfr) 7 6 5 4 3 2 1 0 pwm4e esync bmod phlt updt uall nops1 nops0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h pwm4e control timer 4 mode 0 select timer/counter or capture mode of timer 4 1 select 10-bit pwm mode of timer 4 esync select the operation of external sync with the blnk pin 0 disable external sync operation 1 enable external sync operation (the all pwm4xa/pwm4xb pins are high-impedance outputs on rising edge of the blnk input pin. where x= a, b and c) bmod control back-to-back mode operation 0 disable back-to-back mode (up count only) 1 enable back-to-back mode (up/down count only) phlt control timer 4 pwm operation 0 run 10-bit pwm 1 stop 10-bit pwm (counter hold and output disable) updt select the update timer of t4ppr/t4adr/t4bdr/t4cdr 0 update at period match of t4cnt and t4ppr 1 update at any time when written uall control update all duty re gisters (t4adr/t4bdr/t4cdr) 0 write a duty register separately 1 wrtie all duty registers via timer 4 pwm a dury register (t4adr) nops[1:0] select on-overlap prescaler nops1 nops0 description 0 0 f pwm /1 0 1 f pwm /2 1 0 f pwm /4 1 1 f pwm /8 note) where the f pwm is the clock frequency of the timer 4 pwm.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 167 t4pcr2 (timer 4 pwm control register 2) : 1004h (esfr) 7 6 5 4 3 2 1 0 forca ? paaoe paboe pbaoe pbboe pcaoe pcboe r/w ? r/w r/w r/w r/w r/w r/w initial value : 00h forca control the pwm outputs mode 0 6-channel mode (the pwm4xa/pwm4xb pins are output according to the t4xdr registers, respectively. where x = a, b and c) 1 force a-channel mode (the all pwm4xa/pwm4xb pins are output according to the only t4adr registers. where x = a, b and c) paaoe select channel pwm4aa operation 0 disable pwm4aa output 1 enable pwm4aa output paboe select channel pwm4ab operation 0 disable pwm4ab output 1 enable pwm4ab output pbaoe select channel pwm4ba operation 0 disable pwm4ba output 1 enable pwm4ba output pbboe select channel pwm4bb operation 0 disable pwm4bb output 1 enable pwm4bb output pcaoe select channel pwm4ca operation 0 disable pwm4ca output 1 enable pwm4ca output pcboe select channel pwm4cb operation 0 disable pwm4cb output 1 enable pwm4cb output
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 168 t4pcr3 (timer 4 pwm control register 3) : 1005h (esfr) 7 6 5 4 3 2 1 0 hzclr polbo polaa polab polba polbb polca polcb r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h hzclr high-impedance output clear bit 0 no effect 1 clear high-impedance output (the pwm4xa/pwm4xb pins are back to output and this bit is automatically cleared to logic ?0?. where x = a, b and c) polbo configure pwm4ab/pwm4bb/pwmcb channel polarity when these pins are disabled 0 these pins are output according to the polarity setting when disable (polab/polbb/polcb bits) 1 these pins are same level as the pwm4xa pins regardless of the polarity setting when disable (polab/polbb/polcb bits, where x = a, b and c) polaa configure pwm4aa channel polarity 0 start at high level (this pin is low level when disable) 1 start at low level (this pin is high level when disable) polab configure pwm4ab channel polarity 0 non-inversion signal of pwm4aa pin 1 inversion signal of pwm4aa pin polba configure pwm4aa channel polarity 0 start at high level (this pin is low level when disable) 1 start at low level (this pin is high level when disable) polbb configure pwm4ab channel polarity 0 non-inversion signal of pwm4ba pin 1 inversion signal of pwm4ba pin polca configure pwm4ca channel polarity 0 start at high level (this pin is low level when disable) 1 start at low level (this pin is high level when disable) polcb configure pwm4cb channel polarity 0 non-inversion signal of pwm4ca pin 1 inversion signal of pwm4ca pin
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 169 t4isr (timer 4 interrupt status register) : 1006h (esfr) 7 6 5 4 3 2 1 0 iovr ibtm icma icmb icmc ? ? ? r/w r/w r/w r/w r/w ? ? ? initial value : 00h iovr timer 4 overflow interrupt status, write ?1? to this bit for clear 0 overflow occurrence 1 overflow no occurrence ibtm timer 4 bottom interrupt status, write ?1? to this bit for clear (in the back-to-back mode) 0 bottom occurrence 1 bottom no occurrence icma timer 4 compare match or pwm a-ch match interrupt staus, write ?1? to this bit for clear 0 compare match or pwm a-ch match occurrence 1 compare match or pwm a-ch match no occurrence icmb timer 4 pwm b-ch match interrupt status, write ?1? to this bit for clear 0 pwm b-ch match occurrence 1 pwm b-ch match no occurrence icmc timer 4 pwm c-ch match interrupt status, write ?1? to this bit for clear 0 pwm c-ch match occurrence 1 pwm c-ch match no occurrence t4msk (timer 4 interrupt mask register) : 1007h (esfr) 7 6 5 4 3 2 1 0 ovrmsk btmmsk cmamsk cmbmsk cmcmsk ? ? ? r/w r/w r/w r/w r/w ? ? ? initial value : 00h ovrmsk control timer 4 overflow interrupt 0 disble overflow interrupt 1 enable overflow interrupt btmmsk control timer 4 bottom interrupt 0 disble bottom interrupt 1 enable bottom interrupt cmamsk control timer 4 compare match or pwm a-ch match interrupt 0 disble compare match or pwm a-ch match interrupt 1 enable compare match or pwm a-ch match interrupt cmbmsk control timer 4 pwm b-ch match interrupt 0 disble pwm b-ch match interrupt 1 enable pwm b-ch match interrupt cmcmsk control timer 4 pwm c-ch match interrupt 0 disble pwm c-ch match interrupt 1 enable pwm c-ch match interrupt
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 170 11.9 buzzer driver 11.9.1 overview the buzzer consists of 8 bit counter, buzzer data register (buzdr), and buzzer control register (buzcr). the square wave (61.035hz~125.0 khz @8mhz) is outputted through p13/seg17/an10/ec1/buzo pin. the buzzer data register (buzdr) controls the bsuzzer frequency (look at the following expression). in buzzer control register (buzcr), buck[1:0] selects source clock divided by prescaler. table 11-15 buzzer frequency at 8 mhz buzdr[7:0] buzzer frequency (khz) buzcr[2:1]=00 buzcr[2:1]=01 buzcr[2:1]=10 buzcr[2:1]=11 0000_0000 125khz 62.5khz 31.25khz 15.625khz 0000_0001 62.5khz 31.25khz 15.625khz 7.812khz ? ? ? ? ? 1111_1101 492.126hz 246.063hz 123.031hz 61.515hz 1111_1110 490.196hz 245.098hz 122.549hz 61.274hz 1111_1111 488.281hz 244.141hz 122.07hz 61.035hz 11.9.2 block diagram pre scaler fx mux counter fx/32 fx/64 fx/128 fx/256 2 buck[1:0] 8-bit up-counter buzdr comparator f/f clear buzo buzen figure 11.48 buzzer driver block diagram 1) (buzdr ratio prescaler 2 frequency oscillator (hz)f buz ? ? ? ?
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 171 11.9.3 register map table 11-16 buzzer driver register map name address dir default description buzdr 8fh r/w ffh buzzer data register buzcr 97h r/w 00h buzzer control register 11.9.4 buzzer driver register description buzzer driver consists of buzzer data register (buzdr) and buzzer control register (buzcr). 11.9.5 register description for buzzer driver buzdr (buzzer data register) : 8fh 7 6 5 4 3 2 1 0 buzdr7 buzdr6 buzdr5 buzdr4 buzdr3 buzdr2 buzdr1 buzdr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh buzdr[7:0] this bits control the buzzer frequency its resolution is 00h ~ ffh buzcr (buzzer control register) : 97h 7 6 5 4 3 2 1 0 ? ? ? ? ? buck1 buck0 buzen ? ? ? ? ? r/w r/w r/w initial value : 00h buck[1:0] buzzer driver source clock selection buck1 buck0 description 0 0 fx/32 0 1 fx/64 1 0 fx/128 1 1 fx/256 buzen buzzer driver operation control 0 buzzer driver disable 1 buzzer driver enable note) fx: system clock oscillation frequency.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 172 11.10 spi 2 11.10.1 overview there is serial peripheral interface (spi 2) one channel in z51f3220. the spi 2 allows synchronous serial data transfer between the external serial devices. it can do full-duplex communication by 4-wire (mosi2, miso2, sck2, ss2), support master/slave mode, can select serial clock (sck2) polarity, phase and whether lsb first data transfer or msb first data transfer. 11.10.2 block diagram p r e s c a l e r fx m u x fx/4 fx/8 fx/32 fx/64 fx/128 fx/16 fx/2 sck control ms sck 2 3 spicr[2:0] m u x ms cpha edge detector cpol spi control circuit wcol spien int_ack clear to interrupt block spiifr 8-bit shift register m u x ms spidr (8-bit) flsb 8 d e p miso2 mosi2 ss2 ss control ms ssena internal bus line fxch figure 11.49 spi 2 block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 173 11.10.3 data transmit / receive operation user can use spi 2 for serial data communication by following step 1. select spi 2 operation mode(master/slave, polarity, phase) by control register spicr. 2. when the spi 2 is configured as a master, it selects a slave by ss2 signal (active low). when the spi 2 is configured as a slave, it is selected by ss2 signal incoming from master 3. when the user writes a byte to the data register spidr, spi 2 will start an operation. 4. in this time, if the spi 2 is configured as a master, serial clock will come out of sck2 pin. and master shifts the eight bits into the slave (transmit), slave shifts the eight bits into the master at the same time (receive). if the spi 2 is configured as a slave, serial clock will come into sck2 pin. and slave shifts the eight bits into the master (transmit), master shifts the eight bits into the slave at the same time (receive). 5. when transmit/receive is done, spiifr bit will be set. if the spi 2 interrupt is enabled, an interrupt is requested. and spiifr bit is cleared by hardware when executing the corresponding interrupt. if spi 2 interrupt is disable, spiifr bit is cleared when user read the status register spisr, and then access (read/write) the data register spidr. 11.10.4 ss2 pin function 1. when the spi 2 is configured as a slave, the ss2 pin is always input. if low signal come into ss2 pin, the spi 2 logic is active. and if ?high? signal come into ss2 pin, the spi 2 logic is stop. in this time, spi 2 logic will be reset, and invalidated any received data. 2. when the spi 2 is configured as a master, the user can select the direction of the ss2 pin by port direction register (p17io). if the ss2 pin is configured as an output, user can use general p17io output mode. if the ss2 pin is configured as an input, ?high? signal must come into ss2 pin to guarantee master operation. if ?low? signal come into ss2 pin, the spi 2 logic interprets this as another master selecting the spi 2 as a slave and starting to send data to it. to avoid bus contention, msb bit of spicr will be cleared and the spi 2 becomes a slave and then, spiifr bit of spisr will be set, and if the spi 2 interrupt is enabled, an interrupt is requested. notes) - when the ss2 pin is configured as an output at master mode, ss2 pin?s output value is defined by user?s software (p17io). before spicr setting, the direction of ss2 pin must be defined - if you don?t need to use ss2 pin, clear the ssena bit of spisr. so, you can use disa bled pin by p17io freely. in this case, ss2 signal is driven by ?high? or ?low? internally. in other words, master is ?high?, salve is ?low? - when ss2 pin is configured as input, if ?high? signal come into ss2 pin, ss_high flag bit will be set. and you can clear it by writing ?0?.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 174 11.10.5 spi 2 timing diagram sck2 (cpol = 1) miso2/mosi2 (output) mosi2/miso2 (input) d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sck2 (cpol = 0) ss2 spiifr figure 11.50 spi 2 transmit/receive timing diagram at cpha = 0 sck2 (cpol = 1) miso2/mosi2 (output) mosi2/miso2 (input) d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sck2 (cpol = 0) ss2 spiifr figure 11.51 spi 2 transmit/receive timing diagram at cpha = 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 175 11.10.6 register map table 11-17 spi 2 register map name address dir default description spisr b7h r/w 00h spi 2 status register spidr b6h r/w 00h spi 2 data register spicr b5h r/w 00h spi 2 control register 11.10.7 spi 2 register description the spi 2 register consists of spi 2 control register (spicr), spi 2 status register (spisr) and spi 2 data register (spidr) 11.10.8 register description for spi 2 spidr (spi 2 data register) : b6h 7 6 5 4 3 2 1 0 spidr7 spidr6 spidr5 spidr4 spidr3 spidr2 spidr1 spidr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h spidr [7:0] spi 2 data when it is written a byte to this data register, the spi 2 will start an operation.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 176 spisr (spi 2 status register) : b7h 7 6 5 4 3 2 1 0 spiifr wcol ss_high ? fxch ssena ? ? r/w r r/w ? r/w r/w ? ? initial value : 00h spiifr when spi 2 interrupt occurs, this bit becomes ?1?. if spi 2 interrupt is enable, this bit is auto cleared by int_ack signal. and if spi 2 interrupt is disable, this bit is cleared when the status register spisr is read, and then access (read/write) the data register spidr 0 spi 2 interrupt no generation 1 spi 2 interrupt generation wcol this bit is set if any data are written to the data register spidr during transfer. this bit is cleared when the status register spisr is read, and then access (read/write) the data register spidr 0 no collision 1 collision ss_high when the ss2 pin is configured as input, if ?high? signal comes into the pin, this flag bit will be set. 0 cleared when ?0? is written 1 no effect when ?1? is written fxch spi 2 port function exchange control bit. 0 no effect 1 exchange mosi2 and miso2 function ssena this bit controls the ss2 pin operation 0 disable 1 enable (the p17 should be a normal input)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 177 spicr (spi 2 control register) : b5h 7 6 5 4 3 2 1 0 spien flsb ms cpol cpha dscr scr1 scr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h spien this bit controls the spi 2 operation 0 disable spi 2 operation 1 enable spi 2 operation flsb this bit selects the data transmission sequence 0 msb first 1 lsb first ms this bit selects whether master or slave mode 0 slave mode 1 master mode cpol cpha this two bits control the serial clock (sck2) mode. clock polarity(cpol) bit determine sck2?s value at idle mode. clcok phase (cpha) bit determine if data are sampled on the leading or trailing edge of sck2. cpol cpha leading edge trailing edge 0 0 sample (rising) setup (falling) 0 1 setup (rising) sample (falling) 1 0 sample (falling) setup (rising) 1 1 setup (falling) sample (rising) dscr scr[2:0] these three bits select the sck2 rate of the device configured as a master. when dscr bit is written one, sck2 will be doubled in master mode. dscr scr1 scr0 sck2 frequency 0 0 0 fx/4 0 0 1 fx/16 0 1 0 fx/64 0 1 1 fx/128 1 0 0 fx/2 1 0 1 fx/8 1 1 0 fx/32 1 1 1 fx/64
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 178 11.11 12-bit a/d converter 11.11.1 overview the analog-to-digital converter (a/d) allows conversion of an analog input signal to corresponding 12-bit digital value. the a/d module has eight analog inputs. the output of the multiplexer is the input into the converter which generates the result through successive approximation. the a/d module has four registers which are the a/d converter control high register (adccr h), a/d converter control low register (adccrl), a/ d converter data high register (adcdrh), and a/d converter data low register (adcdrl). the channels to be converted are selected by setting adsel[3:0]. to execute a/d conversion, trig[2:0] bits should be set to ?xxx?. the register adcdrh and adcdrl contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcdrh and adcdrl, the a/d conv ersion status bit aflag is set to ?1?, and the a/d interrupt is set. during a/d conversion, aflag bit is read as ?0?. 11.11.2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set up a/d conversion. therefore, total of 58 clocks are required to complete a 12-bit conversion: when fxx/8 is selected for conversion clock with a 12mhz fxx clock frequency, one clock cycle is 0.66 s. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 12 bits + set-up time = 58 clocks, 58 clock 0.66 s = 38.28 s at 1.5 mhz (12 mhz/8) note) the a/d converter needs at least 20 s for conversion time. so you must set the conversion time more than 20 s .
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 179 11.11.3 block diagram clock selector adcdrh (r), adcdrl (r) - + control logic comparator adsel[3:0] (select one input pin of the assigned pins) adclk input pins m u x an0 reference voltage avref avss an1 an2 an14 an15 adcifr aflag int_ack clear clear to interrupt block mux vdd start m u x t4 a match event signal t4 b match event signal t4 c match event signal refsel trig[2:0] 3 adst t1 a match signal t4 overflow event signal figure 11.52 12-bit adc block diagram an0~ an15 analog input 0~1000pf figure 11.53 a/d analog input pin with capacitor avref analog power input 22uf figure 11.54 a/d power (avref) pin with capacitor
mc96f6432 ps029902-0212 p r e l i m i n a r y 180 11.11.4 adc operation align bit set 0 adcdrh7 adcdrh6 adcdrh5 adcdrh4 adcdrh3 adcdrh2 adcdrh1 adcdrh0 adcdrl7 adcdrl6 adcdrl5 adcdrl4 adco11 adco10 adco9 adco8 adco7 adco6 adco5 adco4 adco3 adco2 adco1 adco0 align bit set 1 adcdrh3 adcdrh2 adcdrh1 adcdrh0 adcdrl7 adcdrl6 adcdrl5 adcdrl4 adcdrl3 adcdrl2 adcdrl1 adcdrl0 adco11 adco10 adco9 adco8 adco7 adco6 adco5 adco4 adco3 adco2 adco1 adco0 adcdrl[7:0] adcdrl[3:0] adcdrl[7:4] bits are 0 adcdrh[7:0] adcdrl[7:4] adcdrl[3 :0] bits are 0 figure 11.55 adc operation for align bit
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 182 figure 11.56 a/d converter operation flow 11.11.5 register map table 11-18 adc register map name address dir default description a dcdrh 9fh r xxh a/d converter data high register a dcdrl 9eh r xxh a/d converter data low register a dccrh 9dh r/w 00h a/d converter control high register a dccrl 9ch r/w 00h a/d converter control low register 11.11.6 adc register description the adc register consists of a/d converter data hi gh register (adcdrh), a/d converter data low register (adcdrl), a/d converter control high register (adccrh) and a/d converter control low register (adccrl). set adccrh set adccrl aflag = 1? converting start read adcdrh/l adc end select adc clock and data align bit. adc enable & select an input channel. start adc conversion. if conversion is completed, aflag is set ?1? and adc interrupt is occurred. after conversion is completed, read adcdrh and adcdrl. y n
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 183 11.11.7 register description for adc adcdrh (a/d converter data high register) : 9fh 7 6 5 4 3 2 1 0 addm11 addm10 addm9 addm8 addm7 addl11 addm6 addl10 addm5 addl9 addm4 addl8 r r r r r r r r initial value : xxh addm[11:4] msb align, a/d converter high data (8-bit) addl[11:8] lsb align, a/d converter high data (4-bit) adcdrl (a/d converter data low register) : 9eh 7 6 5 4 3 2 1 0 addm3 addl7 addm2 addl6 addm1 addl5 addm0 addl4 addl3 addl2 addl1 addl0 r r r r r- r r r initial value : xxh addm[3:0] msb align, a/d converter low data (4-bit) addl[7:0] lsb align, a/d converter low data (8-bit) adccrh (a/d converter high register) : 9dh 7 6 5 4 3 2 1 0 adcifr ? trig2 trig1 trig0 align cksel1 cksel0 r/w ? r/w r/w r/w r/w r/w r/w initial value : 00h adcifr when adc interrupt occurs, this bit becomes ?1?. for clearing bit, write ?0? to this bit or auto clear by int_ack signal. 0 adc interrupt no generation 1 adc interrupt generation trig[2:0] a/d trigger signal selection trig2 trig1 trig0 description 0 0 0 adst 0 0 1 timer 1 a match signal 0 1 0 timer 4 overflow event signal 0 1 1 timer 4 a match event signal 1 0 0 timer 4 b match event signal 1 0 1 timer 4 c match event signal other values not used align a/d converter data align selection. 0 msb align (adcdrh[7:0], adcdrl[7:4]) 1 lsb align (adcrdh[3:0], adcdrl[7:0]) cksel[1:0] a/d converter clock selection cksel1 cksel0 description 0 0 fx/1 0 1 fx/2 1 0 fx/4 1 1 fx/8
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 184 adccrl (a/d converter counter low register) : 9ch 7 6 5 4 3 2 1 0 stby adst refsel aflag adsel3 adsel2 adsel1 adsel0 r/w r/w r/w r r/w r/w r/w r/w initial value : 00h stby control operation of a/d (the adc module is automatically disabled at stop mode) 0 adc module disable 1 adc module enable adst control a/d conversion stop/start. 0 no effect 1 adc conversion start and auto clear refsel a/d converter reference selection 0 internal reference (vdd) 1 external reference (avref) aflag a/d converter operation state (this bit is cleared to ?0? when the stby bit is set to ?0? or when the cpu is at stop mode) 0 during a/d conversion 1 a/d conversion finished adsel[3:0] a/d converter input selection adsel3 adsel2 adsel1 ad sel0 description 0 0 0 0 an0 0 0 0 1 an1 0 0 1 0 an2 0 0 1 1 an3 0 1 0 0 an4 0 1 0 1 an5 0 1 1 0 an6 0 1 1 1 an7 1 0 0 0 an8 1 0 0 1 an9 1 0 1 0 an10 1 0 1 1 an11 1 1 0 0 an12 1 1 0 1 an13 1 1 1 0 an14 1 1 1 1 an15
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 185 11.12 usi0 (uart + spi + i2c) 11.12.1 overview the usi0 consists of usi0 control register1/2/3/4, usi0 status register 1/2, usi0 baud-rate generation register, usi0 data register, usi0 sda hold time register, usi0 scl high period register, usi0 scl low period register, and usi0 slave address register (usi0cr1, usi0cr2, usi0cr3, usi0cr4, usi0st1, usi0st2, usi0bd, usi0dr, usi0sdhr, usi0schr, usi0sclr, usi0sar). the operation mode is selected by the operatio n mode of usi0 selectio n bits (usi0ms[1:0]). it has four operating modes: - asynchronous mode (uart) - synchronous mode - spi mode - i2c mode
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 186 11.12.2 usi0 uart mode the universal synchronous and asynchronous serial receiver and transmitter (uart) is a highly flexible serial communication device. the main features are listed below. - full duplex operation (independent serial receive and transmit registers) - asynchronous or synchronous operation - baud rate generator - supports serial frames with 5,6,7,8, or 9 data bits and 1 or 2 stop bits - odd or even parity generation and parity check supported by hardware - data overrun detection - framing error detection - three separate interrupts on tx complete, tx data register empty and rx complete - double speed asynchronous communication mode usi0 has three main parts of clock generator, transmitter and receiver. the clock generation logic consists of synchronization logic for external clock inut used by synchronous or spi slave operation, and the baud rate generator for asynchronous or master (synchronous or spi) operation. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows continuous transfer of data without any delay between frames. the receiver is the most complex part of the uart module due to its clock and data recovery units. the recovery unit is used for asynchronous data reception. in addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive fifo (usi0dr) and control logic. the receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 187 11.12.3 usi0 uart block diagram rxd0 rx control clock recovery receive shift register (rxsr) data recovery dor0/pe0/fe0 checker usi0dr[0], usi0rx8[0], (rx) usi0dr[1], usi0rx8[1], (rx) txd0 tx control stop bit generator parity generator transmit shift register (txsr) usi0dr, usi0tx8, (tx) usi0p[1:0] m u x loops 0 txc0 txcie0 drie0 dre0 empty signal to interrupt block int_ack clear rxc0 rxcie0 wakeie0 wake0 at stop mode to interrupt block sclk (fx: system clock) low level detector 2 usi0s[2:0] 3 usi0s[2:0] 3 txe0 rxe0 dbls0 usi0sb baud rate generator usi0bd i n t e r n a l b u s l i n e sck0 ack control clock sync logic master usi0ms[1:0] m u x m u x usi0ms[1:0] usi0ms[1:0] 2 2 2 figure 11.57 usi0 uart block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 188 11.12.4 usi0 clock generation figure 11.58 clock generation block diagram (usi0) the clock generation logic generates the base clock for the transmitter and receiver. the usi0 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the clock generation scheme for master spi and slave spi mode is the same as master synchronous and slave synchronous operation mode. the usi0ms[1:0] bits in usi0cr1 register selects asynchronous or synchronous operation. asynchronous double speed mode is controlled by the dbls0 bit in the usi0cr2 register. the master0 bit in usi0cr3 register controls whether the clock source is internal (master mode, output pin) or external (slave mode, input pin). the sck0 pin is active only when the usi0 operates in synchronous or spi mode. following table shows the equations for calculating the baud rate (in bps). table 11-19 equations for calculating usi0 baud rate register setting operating mode equation for calculating baud rate asynchronous normal mode (dbls0=0) baud rate fx 16usi0bd 1 asynchronous double speed mode (dbls0=1) baud rate fx 8usi0bd 1 synchronous or spi master mode baud rate fx 2usi0bd 1 sck0 prescaling up-counter usi0bd /2 /8 sync register m u x m u x m u x m u x /2 edge detector sclk f sclk (usi0bd+1) txclk rxclk usi0ms[1:0] dbls0 master0 cpol0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 189 11.12.5 usi0 external clock (sck0) external clocking is used in the synchronous mode of operation. external clock input from the sck0 pin is sampled by a synchronization logic to remove meta-stability. the output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver. this process introduces two cpu clock period delay. the maximum frequency of the external sck0 pin is limited up-to 1mhz. 11.12.6 usi0 synchronous mode operation when synchronous or spi mode is used, the sck0 pin will be used as either clock input (s lave) or clock output (master). data sampling and transmitter is issued on the different edge of sck0 clock each other. for example, if data input on rxd0 (miso0 in spi mode) pin is sampled on the rising edge of sck0 clock, data output on txd0 (mosi0 in spi mode) pin is altered on the falling edge. the cpol0 bit in usi0cr1 register selects which sck0 clock edge is used for data sampling and which is used for data change. as shown in the figure below, when cpol0 is zero, the data will be changed at rising sck0 edge and sampled at falling sck0 edge. figure 11.59 synchronous mode sck0 timing (usi0) sck0 txd0/rxd0 cpol0 = 1 txd0/rxd0 sck0 cpol0 = 0 sample sample
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 190 11.12.7 usi0 uart data format a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. the uart supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit (lsb). then the next data bits, up to nine, are succeeding, ending with the most significant bit (msb). if parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. a high-to-low transition on data pin is considered as start bit. when a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. the idle means high state of data pin. the following figure shows the possible combinations of the frame formats. bits inside brackets are optional. figure 11.60 frame format (usi0) 1 data frame consists of the following bits ? idle no communication on communication line (txd0/rxd0) ? st start bit (low) ? dn data bits (0~8) ? parity bit ------------ even parity, odd parity, no parity ? stop bit(s) ---------- 1 bit or 2 bits the frame format used by the uart is set by the us i0s[2:0], usi0pm[1:0] bits in usi0cr1 register and usi0sb bit in usi0cr3 register. the transmitter and receiver use the same setting. 11.12.8 usi0 uart parity bit the parity bit is calculated by doing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive-o is inverted. the parity bit is located between the msb and first stop bit of a serial frame. p even = d n-1 ^ ? ^ d 3 ^ d 2 ^ d 1 ^ d 0 ^ 0 p odd = d n-1 ^ ? ^ d 3 ^ d 2 ^ d 1 ^ d 0 ^ 1 p even : parity bit using even parity p odd : parity bit using odd parity d n : data bit n of the character [d7] [d6] [d5] d4 d3 d2 d1 d0 [d8] [p] idle st sp1 [sp2] idle / st 1 data frame character bits
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 191 11.12.9 usi0 uart transmitter the uart transmitter is enabled by setting the txe0 bit in usi0cr2 register. when the transmitter is enabled, the txd0 pin should be set to txd0 function for the serial output pin of uart by the p4fsr[3:2]. the baud-rate, operation mode and frame format must be setup once before doing any transmission. in synchronous operation mode, the sck0 pin is used as transmission clock, so it should be selected to do sck0 function by p4fsr[5:4] . 11.12.9.1 usi0 uart sending tx data a data transmission is initiated by loading the transmit buffer (usi0dr register i/o location) with the data to be transmitted. the data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. the shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. when the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers. if the 9-bit characters are used in asynchronous or synchronous operation mode, the ninth bit must be written to the usi0tx8 bit in usi0cr3 register before it is loaded to the transmit buffer (usi0dr register). 11.12.9.2 usi0 uart transmit ter flag and interrupt the uart transmitter has 2 flags which indicate its state. one is uart data register empty flag (dre0) and the other is transmit complete flag (txc0). both flags can be interrupt sources. dre0 flag indicates whether the transmit buffer is ready to receive new data. this bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. and also this flag can be cleared by writing ?0? to this bit position. writing ?1? to this bit position is prevented. when the data register empty interrupt enable (drie0) bit in usi0cr2 register is set and the global interrupt is enabled, usi0st1 status register empty interrupt is generated while dre0 flag is set. the transmit complete (txc0) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. the txc0 flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ?0? to txc0 bit in usi0st1 register. when the transmit complete interrupt enable (txcie0) bit in usi0cr2 register is set and the global interrupt is enabled, uart transmit complete interrupt is generated while txc0 flag is set.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 192 11.12.9.3 usi0 uart parity generator the parity generator calculates the parity bit for the serial frame data to be sent. when parity bit is enabled (usi0pm1=1), the transmitter control logic inserts the parity bit between the msb and the first stop bit of the frame to be sent. 11.12.9.4 usi0 uart disabling transmitter disabling the transmitter by clearing the txe0 bit will not become effective until ongoing transmission is completed. when the transmitter is disabled, the txd0 pin can be used as a normal general purpose i/o (gpio). 11.12.10 usi0 uart receiver the uart receiver is enabled by setting the rxe0 bit in the usi0cr2 register. when the receiver is enabled, the rxd0 pin should be set to rxd0 function for the serial input pin of uart by p4fsr[1:0]. the baud-rate, mode of operation and frame format must be set before serial reception. in synchronous or spi operation mode the sck0 pin is used as transfer clock, so it should be selected to do sck0 function by p4fsr[5:4]. in spi operation mode the ss0 input pin in slave mode or can be configured as ss0 output pin in master mode. this can be done by setting usi0 ssen bit in usi0cr3 register. 11.12.10.1 usi0 uart receiving rx data when uart is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a valid start bit (low) on rxd0 pin. each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of sck0 (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. even if there?s 2 nd stop bit in the frame, the 2 nd stop bit is ignored by the receiver. that is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. the receive buffer is read by reading the usi0dr register. if 9-bit characters are used (usi0s[2:0] = ?111?), the ninth bit is stored in the usi0rx8 bit position in the usi0cr3 register. the 9 th bit must be read from the usi0rx8 bit before reading the low 8 bits from the usi0dr register. likewise, the error flags fe0, dor0, pe0 must be read before reading the data from usi0dr register. it?s because the error flags are stored in the same fifo position of the receive buffer.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 193 11.12.10.2 usi0 uart receiver flag and interrupt the uart receiver has one flag that indicates the receiver state. the receive complete (rxc0) flag indicates whether there are unread data in the receive buffer. this flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. if the receiver is disabled (rxe0=0), the receiver buffer is flushed and the rxc0 flag is cleared. when the receive complete interrupt enable (rxcie0) bit in the usi0cr2 register is set and global interrupt is enabled, the uart receiver complete interrupt is generated while rxc0 flag is set. the uart receiver has three error flags which are frame error (fe0), data overrun (dor0) and parity error (pe0). these error flags can be read from the usi0st1 register. as received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. so, before reading received data from usi0dr register, read the usi0st1 register first which contains error flags. the frame error (fe0) flag indicates the state of the first stop bit. the fe0 flag is ?0? when the stop bit was correctly detected as ?1?, and the fe0 flag is ?1? when the stop bit was incorrect, i.e. detected as ?0?. this flag can be used for detecting out-of-sync conditions between data frames. the data overrun (dor0) flag indicates data loss due to a receive buffer full condition. dor0 occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. after the dor0 flag is set, all the incoming data are lost. to prevent data loss or clear this flag, read the receive buffer. the parity error (pe0) flag indicates that the frame in the receive buffer had a parity error when received. if parity check function is not enabled (usi0pm1=0), the pe bit is always read ?0?. 11.12.10.3 usi0 uart parity checker if parity bit is enabled (usi0pm1=1), the parity checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.12.10.4 usi0 uart disabling receiver in contrast to transmitter, disabling the receiver by clearing rxe0 bit makes the receiver inactive immediately. when the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the rxd0 pin can be used as a normal general purpose i/o (gpio).
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 194 11.12.10.5 usi0 asynchronous data reception to receive asynchronous data frame, the uart includes a clock and data recovery unit. the clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the rxd0 pin. the data recovery logic samples and low pass filters the incoming bits, and this removes the noise of rxd0 pin. the next figure illustrates the sampling process of the start bit of an incoming frame. the sampling rate is 16 times of the baud-rate in normal mo de and 8 times the aud-rate for do uble speed mode (dbls0=1). the horizontal arrows show the synchronization variation due to the asynchronous sampling process. note that larger time variation is shown when using the double speed mode. figure 11.61 asynchronous start bit sampling (usi0) when the receiver is enabled (rxe0=1), the clock recovery logic tries to find a high-to-low transition on the rxd0 line, the start bit condition. after detecting high to low transition on rxd0 line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. if more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. and the data recovery can begin. the synchronization process is repeated for each start bit. as described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. data recovery process is almost similar to the clock recovery process. the data recovery logic samples 16 times for each incoming bits for normal mode and 8 times for double speed mode, and uses sample 8, 9 and 10 to decide data value. if more than 2 samples have low levels, the received bit is considered to a logic ?0? and if more than 2 samples have high levels, the received bit is considered to a logic ?1?. the data recovery process is then repeated until a complete frame is received including the first stop bit. the decided bit value is stored in the receive shift register in order. note that the receiver only uses the first stop bit of a frame. internally, after receiving the first stop bit, the receiver is in idle state and waiting to find start bit. figure 11.62 asynchronous sampling of data and parity bit (usi0) rxd0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 bit n 1 2 3 4 5 6 7 8 1 sample (dbls0 = 0) sample (dbls0 = 1) rxd0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 idle bit0 start 0 1 2 3 4 5 6 7 8 1 2 sample (dbls0 = 0) sample (dbls0 = 1)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 195 the process for detecting stop bit is like clock and data recovery process. that is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (fe0) flag is set. after deciding whether the first stop bit is valid or not, the receiver goes to idle state and monitors the rxd0 line to check a valid high to low transition is detected (start bit detection). figure 11.63 stop bit sampling and next start bit sampling (usi0) rxd0 1 2 3 4 5 6 7 8 9 10 11 12 13 stop 1 1 2 3 4 5 6 7 sample (dbls0 = 0) sample (dbls0 = 1) (a) (b) (c)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 196 11.12.11 usi0 spi mode the usi0 can be set to operate in industrial standard spi compliant mode. the spi mode has the following features. - full duplex, three-wire synchronous data transfer - mater and slave operation - supports all four spi0 modes of operation (mode 0, 1, 2, and 3) - selectable lsb first or msb first data transfer - double buffered transmit and receive - programmable transmit bit rate when spi mode is enabled (usi0ms[1:0]=?11?), the slave select (ss0) pin becomes active low input in slave mode operation, or can be output in master mode operation if usi0ssen bit is set to ?0?. note that during spi mode of operation, the pin rxd0 is renamed as miso0 and txd0 is renamed as mosi0 for compatibility to other spi devices. 11.12.12 usi0 spi clock formats and timing to accommodate a wide variety if synchronus serial peripherals from different manufacturers, the usi0 has a clock polarity bit (cpol0) and a clock phase control bit (cpha0) to select one of four clock formats for data transfers. cpol0 selectively insert an inverter in series with the clock. cpha0 chooses between two different clock phase relationships between the clock and data. note that cpha0 and cpol0 bits in usi0cr1 register have different meanings according to the usi0ms[1:0] bits which decides the operating mode of usi0. table below shows four combinations of cpol0 and cpha0 for spi mode 0, 1, 2, and 3. table 11-20 cpol0 functionality spi mode cpol0 cpha0 leading edge trailing edge 0 0 0 sample (rising) setup (falling) 1 0 1 setup (rising) sample (falling) 2 1 0 sample (falling) setup (rising) 3 1 1 setup (falling) sample (rising)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 197 figure 11.64 usi0 spi clock formats when cpha0=0 when cpha0=0, the slave begins to drive its miso0 output with the first data bit value when ss0 goes to active low. the first sck0 edge causes both the master and the slave to sample the data bit value on their miso0 and mosi0 inputs, respectively. at the second sck0 edge, the usi0 shifts the second data bit value out to the mosi0 and miso0 outputs of the master and slave, respectively. unlike the case of cpha0=1, when cpha0=0, the slave?s ss0 input must go to its inactive high level between transfers. this is because the slave can prepare the first data bit when it detects falling edge of ss0 input. sck0 (cpol0=1) miso0 mosi0 sck0 (cpol0=0) /ss0 out (master) bit7 bit0 /ss0 in (slave) bit6 bit1 ? ? bit2 bit5 bit0 bit7 bit1 bit6 sample msb first lsb first
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 198 figure 11.65 usi0 spi clock formats when cpha0=1 when cpha0=1, the slave begins to drive its miso0 output when ss0 goes active low, but the data is not defined until the first sck0 edge. the first sck0 edge shifts the first bit of data from the shifter onto the mosi0 output of the master and the miso0 output of the slave. the next sck0 edge causes both the master and slave to sample the data bit value on their miso0 and mosi0 inputs, respectively. at the third sck0 edge, the usi0 shifts the second data bit value out to the mosi0 and miso0 output of the master and slave respectively. when cpha0=1, the slave?s ss0 input is not required to go to its inactive high level between transfers. because the spi logic reuses the usi0 resources, spi mode of operation is similar to that of synchronous or asynchronous operation. an spi transfer is initiated by checking for the usi0 data register empty flag (dre0=1) and then writing a byte of data to the usi0dr register. in master mode of operation, even if transmission is not enabled (txe0=0), writing data to the usi0dr register is necessary because the clock sck0 is generated from transmitter block. sck0 (cpol0=1) miso0 mosi0 sck0 (cpol0=0) /ss0 out (master) bit7 bit0 /ss0 in (slave) bit6 bit1 ? ? bit2 bit5 bit0 bit7 bit1 bit6 sample msb first lsb first
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 199 11.12.13 usi0 spi block diagram rxcie0 rx control receive shift register (rxsr) data recovery dor0 checker usi0dr[0], (rx) tx control transmit shift register (txsr) usi0dr, (tx) i n t e r n a l b u s l i n e m u x loops 0 txc0 txcie0 drie0 dre0 empty signal to interrupt block int_ack clear rxc0 baud rate generator usi0bd txe0 sclk (fx: system clock) miso0 mosi0 m u x master0 d e p fxch0 sck0 sck control master0 rxe0 to interrupt block m u x edge detector and controller ss 0 ss control cpha0 cpol0 ord0 ( msb/lsb -1st) usi0dr[1], (rx) usi0 ssen figure 11.66 usi0 spi block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 200 11.12.14 usi0 i2c mode the usi0 can be set to operate in industrial standard serial communicatin protocols mode. the i2c mode uses 2 bus lines serial data line (sda0) and serial clock line (scl0) to exchange data. because both sda0 and scl0 lines are open-drain output, each line needs pull-up resistor. the features are as shown below. - compatible with i2c bus standard - multi-master operation - up to 400khz data transfer read speed - 7 bit address - both master and slave operation - bus busy detection 11.12.15 usi0 i2c bit transfer the data on the sda0 line must be stable during high period of the clock, scl0. the high or low state of the data line can only change when the clock signal on the scl0 line is low. the exceptions are start(s), repeated start(sr) and stop(p) condition where data line changes when clock line is high. figure 11.67 bit transfer on the i2c-bus (usi0) scl0 sda0 data line stable: data valid exept s, sr, p change of data allowed
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 201 11.12.16 usi0 i2c start / repeated start / stop one master can issue a start (s) condition to notice other devices connected to the scl0, sda0 lines that it will use the bus. a stop (p) condition is generated by the master to release the bus lines so that other devices can use it. a high to low transition on the sda0 line while scl0 is high defines a start (s) condition. a low to high transition on the sda0 line while scl0 is high defines a stop (p) condition. start and stop conditions are always generated by the master. the bus is considered to be busy after start condition. the bus is considered to be free again after stop condition, ie, the bus is busy between start and stop condition. if a repeated start condition (sr) is generated instead of stop condition, the bus stays busy. so, the start and repeated start conditions are functionally identical. figure 11.68 start and stop condition (usi0) 11.12.17 usi0 i2c data transfer every byte put on the sda0 line must be 8-bits long. the number of bytes that can be transmitted per transfer is unlimited. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. if a slave can?t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line scl0 low to force the master into a wait state. data transfer then continues when the slave is ready for another byte of data and releases clock line scl0. figure 11.69 data transfer on the i2c-bus (usi0) start or repeated start condition s or sr stop or repeated start condition sr or p msb a cknowledgement si g nal form slave a cknowledgement si g nal form slave byte complete, interru p t within device clock line held low while interru p ts are served. 1 9 1 9 ack ack sda0 scl0 sr p scl0 sda0 start condition s p stop condition
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 202 11.12.18 usi0 i2c acknowledge the acknowledge related clock pulse is generated by the master. the transmitter releases the sda0 line (high) during the acknowledge clock pulse. the receiver must pull down the sda0 line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. when a slave is addressed by a master (address packet), and if it is unable to receive or transmit because it?s performing some real time function, the data line must be left high by the slave. and also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must release the sda0 line (data packet). the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. if a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the slave transmitter must release the data line to allow the master to generate a stop or repeated start condition. figure 11.70 acknowledge on the i2c-bus (usi0) 11.12.19 usi0 i2c synchronization / arbitration clock synchronization is performed using the wired-and connection of i2c interfaces to the scl0 line. this means that a high to low transition on the scl0 line will cause the devices concerned to start counting off their low period and it will hold the scl0 line in that state until the clock high state is reached. however the low to high transition of this clock may not change the state of the scl0 line if another clock is still within its low period. in this way, a synchronized scl0 clock is generated with its low period determined by the device with the longest clock low period, and its high period determined by the one with the shortest clock high period. a master may start a transfer only if the bus is free. two or more masters may generate a start condition. arbitration takes place on the sda0 line, while the scl0 line is at the high level, in such a way that the master which transmits a high level, while another master is transmitting a low level will switch off its data output state because the level on the bus doesn?t correspond to its own level. arbitration continues for many bits until a winning master gets the ownership of i2c bus. its first stage is comparison of the address bits. 1 2 8 data output by transmitter 9 ack nack clock pulse for ack data output by receiver scl0 from master
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 203 figure 11.71 clock synchronization during arbitration procedure (usi0) figure 11.72 arbitration procedure of two masters (usi0) 11.12.20 usi0 i2c operation the i2c is byte-oriented and interrupt based. interrupts are issued after all bus events except for a transmission of a start condition. because the i2c is interrupt based, the application software is free to carry on other operations during a i2c byte transfer. note that when a i2c interrupt is generated, iic0ifr flag in usi0cr4 register is set, it is cleared by writing an any value to usi0st2. when i2c interrupt occurs, the scl0 line is hold low until writing any value to usi0st2. when the iic0ifr flag is set, the usi0st2 contains a value indicating the current state of the i2c bus. according to the value in usi0st2, software can decide what to do next. i2c can operate in 4 modes by configuring master/slave, transmitter/receiver. the operating mode is configured by a winning master. a more detailed explanation follows below. device1 dataout scl0 on bus device2 dataout sda0 on bus s arbitration process not ada p ed device 1 loses a rbitration device1 outputs high high counter reset fast device sclout slow device sclout scl0 wait high counting start high counting
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 204 11.12.20.1 usi0 i2c master transmitter to operate i2c in master transmitter, follow the recommended steps below. 1. enable i2c by setting usi0ms[1:0] bits in usi0cr1 and usi0en bit in usi0cr2. this provides main clock to the peripheral. 2. load sla0+w into the usi0dr where sla0 is address of slave device and w is transfer direction from the viewpoint of the master. for master transmitter, w is ?0?. note that usi0dr is used for both address and data. 3. configure baud rate by writing desired value to both usi0sclr and usi0schr for the low and high period of scl0 line. 4. configure the usi0sdhr to decide when sda0 changes value from falling edge of scl0. if sda0 should change in the middle of scl0 low period, load half the value of usi0sclr to the usi0sdhr. 5. set the startc0 bit in usi0cr4. this transmits a start condition. and also configure how to handle interrupt and ack signal. when the startc0 bit is set, 8-bit data in usi0dr is transmitted out according to the baud-rate. 6. this is ack signal pr ocessing stage for a ddress packet transmitted by master. when 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or not in the 9 th high period of scl0. if the master gains bus mastership, i2c generates gcall interrupt regardless of the reception of ack from the slave device. when i2c loses bus mastership during arbitration process, the mlost0 bit in usi0st2 is set, and i2c waits in idle state or can be operate as an addressed slave. to operate as a slave when the mlost0 bit in usi0st2 is set, the ack0en bit in usi0cr4 must be set and the received 7-bit address must equal to the usi0sla[6:0] bits in usi0sar. in this case i2c operates as a slave transmitter or a slave receiver (go to appropriate section). in this stage, i2c holds the scl0 low. this is because to decide whether i2c continues serial transfer or stops communication. the following steps continue assuming that i2c does not lose mastership during first data transfer. i2c (master) can choose one of the following cases regardless of the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can receive more data from master. in this case, load data to transmit to usi0dr. 2) master stops data transfer even if it receives ack signal from slave. in this case, set the stopc0 bit in usi0cr4. 3) master transmits repeated start condition with not checking ack signal. in this case, load sla0+r/w into the usi0dr and set startc0 bit in usi0cr4. after doing one of the actions above, write any arbitrary to usi0st2 to release scl0 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi0dr and if transfer direction bit is ?1? go to master receiver section. 7. 1-byte of data is being transmitted. during data transfer, bus arbitration continues. 8. this is ack signal processing stage for data packet transmitted by master. i2c holds the scl0 low. when i2c loses bus mastership while transmitting data arbitrating other masters, the mlost0 bit in usi0st2 is set. if then, i2c waits in idle state. when the data in usi0dr is transmitted completely, i2c generates tend0 interrupt. i2c can choose one of the following cases regardless of the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can receive more data from master. in this case, load data to transmit to usi0dr. 2) master stops data transfer even if it receives ack signal from slave. in this case, set the stopc0 bit in usi0cr4. 3) master transmits repeated start condition with not checking ack signal. in this case, load sla0+r/w into the usi0dr and set the startc0 bit in usi0cr4. after doing one of the actions above, write any arbitrary to usi0st2 to release scl0 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi0dr, and if transfer di rection bit is ?1? go to master receiver section. 9. this is the final step for master transmitter function of i2c, handling stop interrupt. the stop bit indicates that data transfer between master and slave is over. to clear usi0st2, write any value to usi0st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 205 the next figure depicts above process for master transmitter operation of i2c. figure 11.73 formats and states in the master transmitter mode (usi0) from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl0 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& other master continues slave receiver (0x1d) or transmitter (0x1f) master receiver sla+w ack data rs stop lost lost& stop lost s or sr sla+r y n 0x0e 0x87 0x86 0x0e ack stop y n 0x0f 0x1d lost? y 0x47 0x1f 0x46 cont? y n stop 0x0f lost p 0x22 p 0x22 0x22 p
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 206 11.12.20.2 usi0 i2c master receiver to operate i2c in master receiver, follow the recommended steps below. 1. enable i2c by setting usi0ms[1:0] bits in usi0cr1 and usi0en bit in usi0cr2. this provides main clock to the peripheral. 2. load sla0+r into the usi0dr where sla is address of slave device and r is transfer direction from the viewpoint of the master. for master receiver, r is ?1?. note that usi0dr is used for both address and data. 3. configure baud rate by writing desired value to both usi0sclr and usi0schr for the low and high period of scl0 line. 4. configure the usi0sdhr to decide when sda0 changes value from falling edge of scl0. if sda0 should change in the middle of scl0 low period, load half the value of usi0sclr to the usi0sdhr. 5. set the startc0 bit in usi0cr4. this transmits a start condition. and also configure how to handle interrupt and ack signal. when the startc0 bit is set, 8-bit data in usi0dr is transmitted out according to the baud-rate. 6. this is ack signal pr ocessing stage for a ddress packet tr ansmitted by master. when 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or not in the 9 th high period of scl0. if the master gains bus mastership, i2c generates gcall interrupt regardless of the reception of ack from the slave device. when i2c loses bus mastership during arbitration process, the mlost0 bit in usi0st2 is set, and i2c waits in idle state or can be operate as an addressed slave. to operate as a slave when the mlost0 bit in usi0st2 is set, the ack0en bit in usi0cr4 must be set and the received 7-bit address must equal to the usi0sla[6:0] bits in usi0sar. in this case i2c operates as a slave transmitter or a slave receiver (go to appropriate section). in this stage, i2c holds the scl0 low. this is because to decide whether i2c continues serial transfer or stops communication. the following steps continue assuming that i2c does not lose mastership during first data transfer. i2c (master) can choose one of the following cases according to the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can prepare and transmit more data to master. configure ack0en bit in usi0cr4 to decide whether i2c acknowledges the next data to be received or not. 2) master stops data transfer because it receives no ack signal from slave. in this case, set the stopc0 bit in usi0cr4. 3) master transmits repeated start condition due to no ack signal from slave. in this case, load sla0+r/w into the usi0dr and set startc0 bit in usi0cr4. after doing one of the actions above, write arbitrary value to usi0st2 to release scl0 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi0dr and if transfer direction bit is ?0? go to master transmitter section. 7. 1-byte of data is being received. 8. this is ack signal processing stage for data packet transmitted by slave. i2c holds the scl0 low. when 1-byte of data is received completely, i2c generates tend0 interrupt. i2c0 can choose one of the following cases according to the rxack0 flag in usi0st2. 1) master continues receiving data from slave. to do this, set ack0en bit in usi0cr4 to acknowledge the next data to be received. 2) master wants to terminate data transfer when it receives next data by not generating ack signal. this can be done by clearing ack0en bit in usi0cr4. 3) because no ack signal is detected, master terminates data transfer. in this case, set the stopc0 bit in usi0cr4. 4) no ack signal is detected, and master transmits repeated start condition. in this case, load sla0+r/w into the usi0dr and set the startc0 bit in usi0cr4. after doing one of the actions above, write arbitrary value to usi0st2 to release scl0 line. in case of 1) and 2), move to step 7. in case of 3), move to step 9 to handle stop interrupt. in case of 4), move to step 6 after transmitting the data in usi0dr, and if transfer direction bit is ?0? go to master transmitter section.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 207 9. this is the final step for master receiver function of i2c, handling stop interrupt. the stop bit indicates that data transfer between master and slave is over. to clear usi0st2, write any value to usi0st2. after this, i2c enters idle state. the processes described above for master receiver operation of i2c can be depicted as th e followin g figure. figure 11.74 formats and states in the master receiver mode (usi0) from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl0 line is held low interrupt after stop command p ack arbitration lost as master and addressed as slave lost& other master continues slave receiver (0x1d) or transmitter (0x1f) master transmitter sla+r ack data rs lost lost& stop lost s or sr sla+w y n 0x0c 0x85 0x84 0x0c ack stop y n 0x0d 0x1d 0x45 0x1f 0x44 lost p 0x20 p 0x20 sr 0x44
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 208 11.12.20.3 usi0 i2c slave transmitter to operate i2c in slave transmitter, follow the recommended steps below. 1. if the main operating clock (sclk) of the system is slower than that of scl0, load value 0x00 into usi0sdhr to make sda0 change within one system clock period from the falling edge of scl0. note that the hold time of sda0 is calculated by sdah x period of sclk where sdah is multiple of number of sclk coming from usi0sdhr. wh en the hold time of sda0 is longe r than the period of sclk, i2c (slave) cannot transmit serial data properly. 2. enable i2c by setting usi0ms[1:0] bits in usi0cr1 , iic0ie bit in usi0cr4 and usi0en bit in usi0cr2. this provides main clock to the peripheral. 3. when a start condition is detected, i2c receives one byte of data and compares it with usi0sla[6:0] bits in usi0sar. if the gcall0 bit in usi0sar is enabled, i2c compares the received data with value 0x00, the general call address. 4. if the received address does not equal to usi0sla[6:0] bits in usi0sar, i2c enters idle state ie, waits for another start condition. else if the address equals to usi0sla[6:0] bits and the ack0en bit is enabled, i2c generates ssel0 interrupt and the scl0 line is held low. note that even if the address equals to usi0sla[6:0] bi ts, when the ack0en bit is disabled , i2c enters idle state. when ssel0 interrupt occurs, load transmit data to usi0dr and write arbitrary value to usi0st2 to release scl0 line. 5. 1-byte of data is being transmitted. 6. in this step, i2c generates tend0 interrupt and holds the scl0 line low regardless of the reception of ack signal from master. slave can select one of the following cases. 1) no ack signal is detected and i2c waits stop or repeated start condition. 2) ack signal from master is detected. load data to transmit into usi0dr. after doing one of the actions above, write arbitrary value to usi0st2 to release scl0 line. in case of 1) move to step 7 to terminate communication. in case of 2) move to step 5. in either case, a repeated start condition can be detected. for that case, move step 4. 7. this is the final step for slave transmitter function of i2c, handling stop interrupt. the stopc0 bit indicates that data transfer between master and slave is over. to clear usi0st2, write any value to usi0st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 209 the next figure shows flow chart for handling slave transmitter function of i2c. figure 11.75 formats and states in the slave transmitter mode (usi0) sla+r ack data lost& s or sr y 0x47 ack stop y n 0x46 p 0x22 idle idle y gcall 0x1f 0x97 0x17 from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl0 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 210 11.12.20.4 usi0 i2c slave receiver to operate i2c in slave receiver, follow the recommended steps below. 1. if the main operating clock (sclk) of the system is slower than that of scl0, load value 0x00 into usi0sdhr to make sda0 change within one system clock period from the falling edge of scl0. note that the hold time of sda0 is calculated by sdah x period of sclk where sdah is multiple of number of sclk coming from usi0sdhr. when the hold time of sda0 is long er than the period of sclk, i2c (slave) cannot transmit serial data properly. 2. enable i2c by setting usi0ms[1:0] bits in usi0cr1, iic0ie bit in usi0cr4 and usi0en bit in usi0cr2. this provides main clock to the peripheral. 3. when a start condition is detected, i2c receives one byte of data and compares it with usi0sla[6:0] bits in usi0sar. if the gcall0 bit in usi0sar is enabled, i2c0 compares the received data with value 0x00, the general call address. 4. if the received address does not equal to sla0bits in usi0sar, i2c enters idle state ie, waits for another start condition. else if the address equals to sla0 bits and the ack0en bit is enabled, i2c generates ssel0 interrupt and the scl0 line is held low. note that even if the address equals to sla0 bits, when the ack0en bit is disabled, i2c enters idle state. when ssel0 interrupt occurs and i2c is ready to receive data, write arbitrary value to usi0st2 to release scl0 line. 5. 1-byte of data is being received. 6. in this step, i2c generates tend0 interrupt and holds the scl0 line low regardless of the reception of ack signal from master. slave can select one of the following cases. 1) no ack signal is detected (ack0en=0) and i2c waits stop or repeated start condition. 2) ack signal is detected (ack0en=1) and i2c can continue to receive data from master. after doing one of the actions above, write arbitrary value to usi0st2 to release scl0 line. in case of 1) move to step 7 to terminate communication. in case of 2) move to step 5. in either case, a repeated start condition can be detected. for that case, move step 4. 7. this is the final step for slave receiver function of i2c, handling stop interrupt. the stopc0 bit indicates that data transfer between master and slave is over. to clear usi0st2, write any value to usi0st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 211 the process can be depicted as following figure when i2c operat es in slave re ceiver mode. figure 11.76 formats and states in the slave receiver mode (usi0) sla+w ack data lost& s or sr y n 0x45 ack stop y n 0x44 p 0x20 idle idle y gcall 0x1d 0x95 0x15 from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl0 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 212 11.12.21 usi0 i2c block diagram receive shift register (rxsr) transmit shift register (txsr) i n t e r n a l b u s l i n e sclk (fx: system clock) sda0 scl0 usi0dr, (rx) vss n-ch vss n-ch scl0 out controller sda0 in/out controller sda hold time register usi0sdhr scl low period register usi0sclr scl high period register usi0schr time generator and time controller usi0dr, (tx) slave address register usi0sar general call and address detector usi0gce stop /start condition generator stopc0 startc0 ack signal generator ack0en rxack0, gcall 0, tend0, stopd0, ssel 0, mlost0, busy0, tmode0 interrupt generator to interrupt block iic0ifr iic0ie note) when the usi0 block is an i2c mode and the corresponding port is an sub-function for scl0/sda0 pin, the scl0/sda0 pins are automatically set to the n-channel open-drain outputs and the input latch is read in the case of reading the pins. the corresponding pull-up resistor is determined by the control register. figure 11.77 usi0 i2c block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 213 11.12.22 register map table 11-21 usi0 register map name address dir default description usi0bd e3h r/w ffh usi0 baud rate generation register usi0dr e5h r/w 00h usi0 data register usi0sdhr e4h r/w 01h usi0 sda hold time register usi0schr e7h r/w 3fh usi0 scl high period register usi0sclr e6h r/w 3fh usi0 scl low period register usi0sar ddh r/w 00h usi0 slave address register usi0cr1 d9h r/w 00h usi0 control register 1 usi0cr2 dah r/w 00h usi0 control register 2 usi0cr3 dbh r/w 00h usi0 control register 3 usi0cr4 dch r/w 00h usi0 control register 4 usi0st1 e1h r/w 80h usi0 status register 1 usi0st2 e2h r 00h usi0 status register 2 11.12.23 usi0 register description usi0 module consists of usi0 baud rate generation register (usi0bd), usi0 data register (usi0dr), usi0 sda hold time register (usi0sdhr), usi0 scl high period register (usi0schr), usi0 scl low period register (usi0sclr), usi0 slave address register (usi0sar), usi0 control register 1/2/3/4 (usi0cr1/2/3/4), usi0 status register 1/2 (usi0st1/2). 11.12.24 register description for usi0 usi0bd (usi0 baud- rate generation register: for uart and spi mode) : e3h 7 6 5 4 3 2 1 0 usi0bd7 usi0bd 6 usi0bd 5 usi0bd 4 usi0bd 3 usi0bd 2 usi0bd 1 usi0bd 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh usi0bd[7:0] the value in this register is used to generate internal baud rate in asynchronous mode or to generate sck0 clock in spi mode. to prevent malfunction, do not write ?0? in asynchronous mode and do not write ?0? or ?1? in spi mode. note) in common with usi0sar register, usi0bd register is used for slave address register when the usi0 i2c mode.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 214 usi0dr (usi0 data register: for uart, spi, and i2c mode) : e5h 7 6 5 4 3 2 1 0 usi0dr7 usi0dr 6 usi0dr 5 usi0dr 4 usi0dr 3 usi0dr 2 usi0dr 1 usi0dr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0dr[7:0] the usi0 transmit buffer and receive buffer share the same i/o address with this data register. the transmit data buffer is the destination for data written to the usi0dr register. reading the usi0dr register returns the contents of the receive buffer. write to this register only when the dre0 flag is set. in spi master mode, the sck clock is generated when data are written to this register. usi0sdhr (usi0 sda hold time register: for i2c mode) : e4h 7 6 5 4 3 2 1 0 usi0sdhr7 usi0sdhr6 usi0sdhr5 usi0sdhr 4 usi0sdhr 3 usi0sdhr 2 usi0sdhr 1 usi0sdhr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0sdhr[7:0] the register is used to control sda0 output timing from the falling edge of sci in i2c mode. note) that sda0 is changed after t sclk x (usi0sdhr+2), in master sda 0 change in the middle of scl0. in slave mode, configure this register regarding the frequency of scl0 from master. the sda0 is changed after tscl k x (usi0sdhr+2) in master mode. so, to insure operation in slave mode, the value t sclk x (usi0sdhr +2) must be smalle r than the period of scl. usi0schr (usi0 scl high period register: for i2c mode) : e7h 7 6 5 4 3 2 1 0 usi0schr7 usi0schr6 usi0schr5 usi0schr 4 usi0schr 3 usi0schr 2 usi0schr 1 usi0schr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0schr[7:0] this register defines the high period of scl0 when it operates in i2c master mode. the base clock is sclk, the system clock, and the period is calculated by the formula: t sclk x (4 x usi0schr +2) where t sclk is the period of sclk. so, the operating frequency of i2c master mode is calculated by the following equation. f i2c = t sclk x ( 4 x ( usi0sclr + usi0schr + 4 )) 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 215 usi0sclr (usi0 scl low period register: for i2c mode) : e6h 7 6 5 4 3 2 1 0 usi0sclr7 usi0sclr6 usi0sclr5 usi0sclr 4 usi0sclr 3 usi0sclr 2 usi0sclr 1 usi0sclr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0sclr[7:0] this register defines the high period of scl0 when it operates in i2c master mode. the base clock is sclk, the system clock, and the period is calculated by the formula: t sclk x (4 x usi0sclr +2) where t sclk is the period of sclk. usi0sar (usi0 slave address register: for i2c mode) : ddh 7 6 5 4 3 2 1 0 usi0sla6 usi0sla5 usi0sla4 usi0sla3 usi0sla2 usi0sla1 usi0sla0 usi0gce r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0sla[6:0] these bits configure the slave address of i2c when it operaties in i2c slave mode. upm[1:0] this bit decides whether i2c allows general call address or not in i2c slave mode. 0 ignore general call address 1 allow general call address
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 216 usi0cr1 (usi0 control register 1: for uart, spi, and i2c mode) : d9h 7 6 5 4 3 2 1 0 usi0ms1 usi0ms0 usi0pm1 usi0pm0 usi0s2 usi0s1 ord0 usi0s0 cpha0 cpol0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi0ms[1:0] selects operation mode of usi0 usi0ms1 usi0ms0 operation mode 0 0 asynchronous mode (uart) 0 1 synchronous mode 1 0 i2c mode 1 1 spi mode usi0pm[1:0] selects parity generation and check methods (only uart mode) usi0pm1 usi0pm0 parity 0 0 no parity 0 1 reserved 1 0 even parity 1 1 odd parity usi0s[2:0] when in asynchronous or synchronous mode of operation, selects the length of data bits in frame usi0s2 usi0s1 usi0s0 data length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 9 bit ord0 this bit in the same bit position with usi0s1. the msb of the data byte is transmitted first when set to ?1? and the lsb when set to ?0? (onl spi mode) 0 lsb-first 1 msb-first cpol0 this bit determines the clock polarity of ack in synchronous or spi mode. 0 txd change@rising edge, rxd change@falling edge 1 txd change@falling edge, rxd change@rising edge cpha0 this bit is in the same bit position with usi0s0. this bit determines if data are sampled on the leading or trailing edge of sck0 (only spi mode). cpol0 cpha0 l eading edge trailing edge 0 0 sample (rising) setup (falling) 0 1 setup (rising) sample (falling) 1 0 sample (falling) setup (rising) 1 1 setup (falling) sample (rising)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 217 usi0cr2 (usi0 control register 2: for uart, spi, and i2c mode) : dah 7 6 5 4 3 2 1 0 drie0 txcie0 rxcie0 wakeie0 txe0 rxe0 usi0en dbls0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h drie0 interrupt enable bit for data register empty (only uart and spi mode). 0 interrupt from dre0 is inhibited (use polling) 1 when dre0 is set, request an interrupt txcie0 interrupt enable bit for transmit complete (only uart and spi mode). 0 interrupt from txc0 is inhibited (use polling) 1 when txc0 is set, request an interrupt rxcie0 interrupt enable bit for receive complete (only uart and spi mode). 0 interrupt from rxc0 is inhibited (use polling) 1 when rxc0 is set, request an interrupt wakeie0 interrupt enable bit for asynchronous wake in stop mode. when device is in stop mode, if rxd0 goes to low level an interrupt can be requested to wake-up system. (only uart mode). at that time the drie0 bit and usi0st1 register value should be set to ?0b? and ?00h?, respectively. 0 interrupt from wake is inhibited 1 when wake0 is set, request an interrupt txe0 enables the transmitter unit (only uart and spi mode). 0 transmitter is disabled 1 transmitter is enabled rxe0 enables the receiver unit (only uart and spi mode). 0 receiver is disabled 1 receiver is enabled usi0en activate usi0 function block by supplying. 0 usi0 is disabled 1 usi0 is enabled dbls0 this bit selects receiver sampling rate (only uart). 0 normal asynchronous operation 1 double speed asynchronous operation
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 218 usi0cr3 (usi0 control register 3: for uart, spi, and i2c mode) : dbh 7 6 5 4 3 2 1 0 master0 loops0 dissck0 usi0ssen fxch0 usi0sb usi0tx8 usi0rx8 r/w r/w r/w r/w r/w r/w r/w r initial value : 00h master0 selects master or slave in spi and synchronous mode operation and controls the direction of sck0 pin 0 slave mode operation (external clock for sck0). 1 master mode operation(internal clock for sck0). loops0 controls the loop back mode of usi0 for test mode (only uart and spi mode) 0 normal operation 1 loop back mode dissck0 in synchronous mode of operation, selects the waveform of sck0 output 0 ack is free-running while uart is enabled in synchronous master mode 1 ack is active while any frame is on transferring usi0ssen this bit controls the ss0 pin operation (only spi mode) 0 disable 1 enable (the ss0 pin should be a normal input) fxch0 spi port function exchange control bit (only spi mode) 0 no effect 1 exchange mosi0 and miso0 function usi0sb selects the length of stop bit in asynchronous or synchronous mode of operation. 0 1 stop bit 1 2 stop bit usi0tx8 the ninth bit of data frame in as ynchronous or synchronous mode of operation. write this bit first before loading the usi0dr register 0 msb (9 th bit) to be transmitted is ?0? 1 msb (9 th bit) to be transmitted is ?1? usi0rx8 the ninth bit of data frame in as ynchronous or synchronous mode of operation. read this bit first before reading the receive buffer (only uart mode). 0 msb (9 th bit) received is ?0? 1 msb (9 th bit) received is ?1?
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 219 usi0cr4 (usi0 control register 4: for i2c mode) : dch 7 6 5 4 3 2 1 0 iic0ifr ? txdlyenb0 iic0ie ack0en imaster0 stopc0 startc0 r ? r/w r/w r/w r r/w r/w initial value : 00h iic0ifr this is an interrupt flag bit for i2c mode. when an interrupt occurs, this bit becomes ?1?. this bit is cleared when write any values in th usi0st2. 0 i2c interrupt no generation 1 i2c interrupt generation txdlyenb0 usi0sdhr register control bit 0 enable usi0sdhr register 1 disable usi0sdhr register iic0ie interrupt enable bit for i2c mode 0 interrupt from i2c is inhibited (use polling) 1 enable interrupt for i2c ack0en controls ack signal generation at ninth scl0 period. 0 no ack signal is generated (sda0 =1) 1 ack signal is generated (sda0 =0) notes) ack signal is output (sda =0) for the following 3 cases. 1. when received address packet equals to usi0sla bits in usi0sar. 2. when received address packet equals to value 0x00 with gcall0 enabled. 3. when i2c operates as a receiver (master or slave) imaster0 represent operating mode of i2c 0 i2c is in slave mode 1 i2c is in master mode stopc0 when i2c is master, stop condition generation 0 no effect 1 stop condition is to be generated startc0 when i2c is master, start condition generation 0 no effect 1 start or repeated start condition is to be generated
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 220 usi0st1 (usi0 status register 1: for uart and spi mode) : e1h 7 6 5 4 3 2 1 0 dre0 txc0 rxc0 wake0 usi0rst dor0 fe0 pe0 r/w r/w r r/w r/w r r/w r/w initial value : 80h dre0 the dre0 flag indicates if the transmit buffer (usi0dr) is ready to receive new data. if dre0 is ?1?, the buffer is empty and ready to be written. this flag can generate a dre0 interrupt. 0 transmit buffer is not empty. 1 transmit buffer is empty. txc0 this flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. this flag is automatically cleared when the interrupt service routine of a txc0 interrupt is executed. this flag can generate a txc0 interrupt. this bit is automatically cleared. 0 transmission is ongoing. 1 transmit buffer is empty and the data in transmit shift register are shifted out completely. rxc0 this flag is set when there are unread data in the receive buffer and cleared when all the data in the receive buffer are read. the rxc0 flag can be used to generate a rxc0 interrupt. 0 there is no data unread in the receive buffer 1 there are more than 1 data in the receive buffer wake0 this flag is set when the rxd0 pin is detected low while the cpu is in stop mode. this flag can be used to generat e a wake0 interrupt. this bit is set only when in asynchronous mode of operation. this bit should be cleared by program software. (only uart mode) 0 no wake interrupt is generated. 1 wake interrupt is generated usi0rst this is an internal reset and only has effect on usi0. writing ?1? to this bit initializes the internal logic of usi0 and this bit is automatically cleared to ?0?. 0 no operation 1 reset usi0 dor0 this bit is set if a data overrun occurs. while this bit is set, the incoming data frame is ignored. this flag is valid until the receive buffer is read. 0 no data overrun 1 data overrun detected fe0 this bit is set if the first stop bit of next character in the receive buffer is detected as ?0?. this bit is valid until the receive buffer is read. (only uart mode) 0 no frame error 1 frame error detected pe0 this bit is set if the next character in the receive buffer has a parity error to be received while parity checking is enabled. this bit is valid until the receive buffer is read. (only uart mode) 0 no parity error 1 parity error detected
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 221 usi0st2 (usi0 status register 2: for i2c mode) : e2h 7 6 5 4 3 2 1 0 gcall0 tend0 stopd0 ssel0 mlost0 busy0 tmode0 rxack0 r r/w r/w r/w r/w r/w r/w r/w initial value : 00h gcall0 (note) this bit has different meaning depending on whether i2c is master or slave. when i2c is a master, this bit represents whether it received aack (address ack) from slave. 0 no aack is received (master mode) 1 aack is received (master mode) when i2c is a slave, this bit is used to indicated general call. 0 general call address is not detected (slave mode) 1 general call address is detected (slave mode) tend0 (note) this bit is set when 1-byte of data is transferred completely 0 1 byte of data is not completely transferred 1 1 byte of data is completely transferred stopd0 (note) this bit is set when a stop condition is detected. 0 no stop condition is detected 1 stop condition is detected ssel0 (note) this bit is set when i2c is addressed by other master. 0 i2c is not selected as a slave 1 i2c is addressed by other master and acts as a slave mlost0 (note) this bit represents the result of bus arbitration in master mode. 0 i2c maintains bus mastership 1 i2c maintains bus mastership during arbitration process busy0 this bit reflects bus status. 0 i2c bus is idle, so a master can issue a start condition 1 i2c bus is busy tmode0 this bit is used to indicate whether i2c is transmitter or receiver. 0 i2c is a receiver 1 i2c is a transmitter rxack0 this bit shows the state of ack signal 0 no ack is received 1 ack is received at ninth scl period note) these bits can be source of interrupt. when an i2c interrupt occurs except for stop mode, the scl0 line is hold low. to release scl0, write rbitrary value to usi0st2. when usi0st2 is written, the tend0, stopd0, ssel0, mlost0, and rxack0 bits are cleared.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 222 11.13 usi1 (uart + spi + i2c) 11.13.1 overview the usi1 consists of usi1 control register1/2/3/4, usi1 status register 1/2, usi1 baud-rate generation register, usi1 data register, usi1 sda hold time register, usi1 scl high period register, usi1 scl low period register, and usi1 slave address register (usi1cr1, usi1cr2, usi1cr3, usi1cr4, usi1st1, usi1st2, usi1bd, usi1dr, usi1sdhr, usi1schr, usi1sclr, usi1sar). the operation mode is selected by the operatio n mode of usi1 selectio n bits (usi1ms[1:0]). it has four operating modes: - asynchronous mode (uart) - synchronous mode - spi mode - i2c mode
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 223 11.13.2 usi1 uart mode the universal synchronous and asynchronous serial receiver and transmitter (uart) is a highly flexible serial communication device. the main features are listed below. - full duplex operation (independent serial receive and transmit registers) - asynchronous or synchronous operation - baud rate generator - supports serial frames with 5,6,7,8, or 9 data bits and 1 or 2 stop bits - odd or even parity generation and parity check supported by hardware - data overrun detection - framing error detection - three separate interrupts on tx complete, tx data register empty and rx complete - double speed asynchronous communication mode usi1 has three main parts of clock generator, transmitter and receiver. the clock generation logic consists of synchronization logic for external clock inut used by synchronous or spi slave operation, and the baud rate generator for asynchronous or master (synchronous or spi) operation. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows continuous transfer of data without any delay between frames. the receiver is the most complex part of the uart module due to its clock and data recovery units. the recovery unit is used for asynchronous data reception. in addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive fifo (usi1dr) and control logic. the receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 224 11.13.3 usi1 uart block diagram rxd1 rx control clock recovery receive shift register (rxsr) data recovery dor1/pe1/fe1 checker usi1dr[0], usi1rx8[0], (rx) usi1dr[1], usi1rx8[1], (rx) txd1 tx control stop bit generator parity generator transmit shift register (txsr) usi1dr, usi1tx8, (tx) usi1p[1:0] m u x loops 1 txc1 txcie1 drie1 dre1 empty signal to interrupt block int_ack clear rxc1 rxcie1 wakeie1 wake1 at stop mode to interrupt block sclk (fx: system clock) low level detector 2 usi1s[2:0] 3 usi1s[2:0] 3 txe1 rxe1 dbls1 usi1sb baud rate generator usi1bd i n t e r n a l b u s l i n e sck1 ack control clock sync logic master usi1ms[1:0] m u x m u x usi1ms[1:0] usi1ms[1:0] 2 2 2 figure 11.78 usi1 uart block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 225 11.13.4 usi1 clock generation figure 11.79 clock generation block diagram (usi1) the clock generation logic generates the base clock for the transmitter and receiver. the usi1 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the clock generation scheme for master spi and slave spi mode is the same as master synchronous and slave synchronous operation mode. the usi1ms[1:0] bits in usi1cr1 register selects asynchronous or synchronous operation. asynchronous double speed mode is controlled by the dbls1 bit in the usi1cr2 register. the master1 bit in usi1cr3 register controls whether the clock source is internal (master mode, output pin) or external (slave mode, input pin). the sck1 pin is active only when the usi1 operates in synchronous or spi mode. following table shows the equations for calculating the baud rate (in bps). table 11-22 equations for calculating usi1 baud rate register setting operating mode equation for calculating baud rate asynchronous normal mode (dbls1=0) baud rate fx 16usi1bd 1 asynchronous double speed mode (dbls1=1) baud rate fx 8usi1bd 1 synchronous or spi master mode baud rate fx 2usi1bd 1 sck1 prescaling up-counter usi1bd /2 /8 sync register m u x m u x m u x m u x /2 edge detector sclk f sclk (usi1bd+1) txclk rxclk usi1ms[1:0] dbls1 master1 cpol1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 226 11.13.5 usi1 external clock (sck1) external clocking is used in the synchronous mode of operation. external clock input from the sck1 pin is sampled by a synchronization logic to remove meta-stability. the output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver. this process introduces two cpu clock period delay. the maximum frequency of the external sck1 pin is limited up-to 1mhz. 11.13.6 usi1 synchronous mode operation when synchronous or spi mode is used, the sck1 pin will be used as either clock input (s lave) or clock output (master). data sampling and transmitter is issued on the different edge of sck1 clock each other. for example, if data input on rxd1 (miso1 in spi mode) pin is sampled on the rising edge of sck1 clock, data output on txd1 (mosi1 in spi mode) pin is altered on the falling edge. the cpol1 bit in usi1cr1 register selects which sck1 clock edge is used for data sampling and which is used for data change. as shown in the figure below, when cpol1 is zero, the data will be changed at rising sck1 edge and sampled at falling sck1 edge. figure 11.80 synchronous mode sck1 timing (usi1) sck1 txd1/rxd1 cpol1 = 1 txd1/rxd1 sck1 cpol1 = 0 sample sample
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 227 11.13.7 usi1 uart data format a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. the uart supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit (lsb). then the next data bits, up to nine, are succeeding, ending with the most significant bit (msb). if parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. a high-to-low transition on data pin is considered as start bit. when a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. the idle means high state of data pin. the following figure shows the possible combinations of the frame formats. bits inside brackets are optional. figure 11.81 frame format (usi1) 1 data frame consists of the following bits ? idle no communication on communication line (txd0/rxd0) ? st start bit (low) ? dn data bits (0~8) ? parity bit ------------ even parity, odd parity, no parity ? stop bit(s) ---------- 1 bit or 2 bits the frame format used by the uart is set by the us i1s[2:0], usi1pm[1:0] bits in usi1cr1 register and usi1sb bit in usi1cr3 register. the transmitter and receiver use the same setting. 11.13.8 usi1 uart parity bit the parity bit is calculated by doing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive-o is inverted. the parity bit is located between the msb and first stop bit of a serial frame. p even = d n-1 ^ ? ^ d 3 ^ d 2 ^ d 1 ^ d 0 ^ 0 p odd = d n-1 ^ ? ^ d 3 ^ d 2 ^ d 1 ^ d 0 ^ 1 p even : parity bit using even parity p odd : parity bit using odd parity d n : data bit n of the character [d7] [d6] [d5] d4 d3 d2 d1 d0 [d8] [p] idle st sp1 [sp2] idle / st 1 data frame character bits
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 228 11.13.9 usi1 uart transmitter the uart transmitter is enabled by setting the txe1 bit in usi1cr2 register. when the transmitter is enabled, the txd1 pin should be set to txd1 function for the serial output pin of uart by the p2fsr[1:0]. the baud-rate, operation mode and frame format must be setup once before doing any transmission. in synchronous operation mode, the sck1 pin is used as transmission clock, so it should be selected to do sck1 function by p2fsr[3:2] . 11.13.9.1 usi1 uart sending tx data a data transmission is initiated by loading the transmit buffer (usi1dr register i/o location) with the data to be transmitted. the data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. the shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. when the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers. if the 9-bit characters are used in asynchronous or synchronous operation mode, the ninth bit must be written to the usi1tx8 bit in usi1cr3 register before it is loaded to the transmit buffer (usi1dr register). 11.13.9.2 usi1 uart transmit ter flag and interrupt the uart transmitter has 2 flags which indicate its state. one is uart data register empty flag (dre1) and the other is transmit complete flag (txc1). both flags can be interrupt sources. dre1 flag indicates whether the transmit buffer is ready to receive new data. this bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. and also this flag can be cleared by writing ?0? to this bit position. writing ?1? to this bit position is prevented. when the data register empty interrupt enable (drie1) bit in usi1cr2 register is set and the global interrupt is enabled, usi1st1 status register empty interrupt is generated while dre1 flag is set. the transmit complete (txc1) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. the txc1 flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ?0? to txc1 bit in usi1st1 register. when the transmit complete interrupt enable (txcie1) bit in usi1cr2 register is set and the global interrupt is enabled, uart transmit complete interrupt is generated while txc1 flag is set.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 229 11.13.9.3 usi1 uart parity generator the parity generator calculates the parity bit for the serial frame data to be sent. when parity bit is enabled (usi1pm1=1), the transmitter control logic inserts the parity bit between the msb and the first stop bit of the frame to be sent. 11.13.9.4 usi1 uart disabling transmitter disabling the transmitter by clearing the txe1 bit will not become effective until ongoing transmission is completed. when the transmitter is disabled, the txd1 pin can be used as a normal general purpose i/o (gpio). 11.13.10 usi1 uart receiver the uart receiver is enabled by setting the rxe1 bit in the usi1cr2 register. when the receiver is enabled, the rxd1 pin should be set to rxd1 function for the serial input pin of uart by p1fsr[1:0]. the baud-rate, mode of operation and frame format must be set before serial reception. in synchronous or spi operation mode the sck1 pin is used as transfer clock, so it should be selected to do sck1 function by p2fsr[3:2]. in spi operation mode the ss1 input pin in slave mode or can be configured as ss1 output pin in master mode. this can be done by setting usi1 ssen bit in usi1cr3 register. 11.13.10.1 usi1 uart receiving rx data when uart is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a valid start bit (low) on rxd1 pin. each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of sck1 (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. even if there?s 2 nd stop bit in the frame, the 2 nd stop bit is ignored by the receiver. that is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. the receive buffer is read by reading the usi1dr register. if 9-bit characters are used (usi1s[2:0] = ?111?), the ninth bit is stored in the usi1rx8 bit position in the usi1cr3 register. the 9 th bit must be read from the usi1rx8 bit before reading the low 8 bits from the usi1dr register. likewise, the error flags fe1, dor1, pe1 must be read before reading the data from usi1dr register. it?s because the error flags are stored in the same fifo position of the receive buffer.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 230 11.13.10.2 usi1 uart receiver flag and interrupt the uart receiver has one flag that indicates the receiver state. the receive complete (rxc1) flag indicates whether there are unread data in the receive buffer. this flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. if the receiver is disabled (rxe1=1), the receiver buffer is flushed and the rxc1 flag is cleared. when the receive complete interrupt enable (rxcie1) bit in the usi1cr2 register is set and global interrupt is enabled, the uart receiver complete interrupt is generated while rxc1 flag is set. the uart receiver has three error flags which are frame error (fe1), data overrun (dor1) and parity error (pe1). these error flags can be read from the usi1st1 register. as received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. so, before reading received data from usi1dr register, read the usi1st1 register first which contains error flags. the frame error (fe1) flag indicates the state of the first stop bit. the fe1 flag is ?0? when the stop bit was correctly detected as ?1?, and the fe1 flag is ?1? when the stop bit was incorrect, i.e. detected as ?0?. this flag can be used for detecting out-of-sync conditions between data frames. the data overrun (dor1) flag indicates data loss due to a receive buffer full condition. dor1 occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. after the dor1 flag is set, all the incoming data are lost. to prevent data loss or clear this flag, read the receive buffer. the parity error (pe1) flag indicates that the frame in the receive buffer had a parity error when received. if parity check function is not enabled (usi1pm1=0), the pe bit is always read ?0?. 11.13.10.3 usi1 uart parity checker if parity bit is enabled (usi1pm1=1), the parity checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.13.10.4 usi1 uart disabling receiver in contrast to transmitter, disabling the receiver by clearing rxe1 bit makes the receiver inactive immediately. when the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the rxd1 pin can be used as a normal general purpose i/o (gpio).
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 231 11.13.10.5 usi1 asynchronous data reception to receive asynchronous data frame, the uart includes a clock and data recovery unit. the clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the rxd1 pin. the data recovery logic samples and low pass filters the incoming bits, and this removes the noise of rxd1 pin. the next figure illustrates the sampling process of the start bit of an incoming frame. the sampling rate is 16 times of the baud-rate in normal mo de and 8 times the aud-rate for double speed mode (dbls1=1). the horizontal arrows show the synchronization variation due to the asynchronous sampling process. note that larger time variation is shown when using the double speed mode. figure 11.82 asynchronous start bit sampling (usi1) when the receiver is enabled (rxe1=1), the clock recovery logic tries to find a high-to-low transition on the rxd1 line, the start bit condition. after detecting high to low transition on rxd1 line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. if more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. and the data recovery can begin. the synchronization process is repeated for each start bit. as described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. data recovery process is almost similar to the clock recovery process. the data recovery logic samples 16 times for each incoming bits for normal mode and 8 times for double speed mode, and uses sample 8, 9 and 10 to decide data value. if more than 2 samples have low levels, the received bit is considered to a logic ?0? and if more than 2 samples have high levels, the received bit is considered to a logic ?1?. the data recovery process is then repeated until a complete frame is received including the first stop bit. the decided bit value is stored in the receive shift register in order. note that the receiver only uses the first stop bit of a frame. internally, after receiving the first stop bit, the receiver is in idle state and waiting to find start bit. figure 11.83 asynchronous sampling of data and parity bit (usi1) rxd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 bit n 1 2 3 4 5 6 7 8 1 sample (dbls1 = 0) sample (dbls1 = 1) rxd1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 idle bit0 start 0 1 2 3 4 5 6 7 8 1 2 sample (dbls1 = 0) sample (dbls1 = 1)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 232 the process for detecting stop bit is like clock and data recovery process. that is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (fe1) flag is set. after deciding whether the first stop bit is valid or not, the receiver goes to idle state and monitors the rxd1 line to check a valid high to low transition is detected (start bit detection). figure 11.84 stop bit sampling and next start bit sampling (usi1) rxd1 1 2 3 4 5 6 7 8 9 10 11 12 13 stop 1 1 2 3 4 5 6 7 sample (dbls1 = 0) sample (dbls1 = 1) (a) (b) (c)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 233 11.13.11 usi1 spi mode the usi1 can be set to operate in industrial standard spi compliant mode. the spi mode has the following features. - full duplex, three-wire synchronous data transfer - mater and slave operation - supports all four spi0 modes of operation (mode 0, 1, 2, and 3) - selectable lsb first or msb first data transfer - double buffered transmit and receive - programmable transmit bit rate when spi mode is enabled (usi1ms[1:0]=?11?), the slave select (ss1) pin becomes active low input in slave mode operation, or can be output in master mode operation if usi1ssen bit is set to ?0?. note that during spi mode of operation, the pin rxd1 is renamed as miso1 and txd1 is renamed as mosi1 for compatibility to other spi devices. 11.13.12 usi1 spi clock formats and timing to accommodate a wide variety if synchronus serial peripherals from different manufacturers, the usi1 has a clock polarity bit (cpol1) and a clock phase control bit (cpha1) to select one of four clock formats for data transfers. cpol1 selectively insert an inverter in series with the clock. cpha1 chooses between two different clock phase relationships between the clock and data. note that cpha1 and cpol1 bits in usi1cr1 register have different meanings according to the usi1ms[1:0] bits which decides the operating mode of usi1. table below shows four combinations of cpol1 and cpha1 for spi mode 0, 1, 2, and 3. table 11-23 cpol1 functionality spi mode cpol1 cpha1 leading edge trailing edge 0 0 0 sample (rising) setup (falling) 1 0 1 setup (rising) sample (falling) 2 1 0 sample (falling) setup (rising) 3 1 1 setup (falling) sample (rising)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 234 figure 11.85 usi1 spi clock formats when cpha1=0 when cpha1=0, the slave begins to drive its miso1 output with the first data bit value when ss1 goes to active low. the first sck1 edge causes both the master and the slave to sample the data bit value on their miso1 and mosi1 inputs, respectively. at the second sck1 edge, the usi1 shifts the second data bit value out to the mosi1 and miso1 outputs of the master and slave, respectively. unlike the case of cpha1=1, when cpha1=0, the slave?s ss1 input must go to its inactive high level between transfers. this is because the slave can prepare the first data bit when it detects falling edge of ss1 input. sck1 (cpol1=1) miso1 mosi1 sck1 (cpol1=0) /ss0 out (master) bit7 bit0 /ss1 in (slave) bit6 bit1 ? ? bit2 bit5 bit0 bit7 bit1 bit6 sample msb first lsb first
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 235 figure 11.86 usi1 spi clock formats when cpha1=1 when cpha1=1, the slave begins to drive its miso1 output when ss1 goes active low, but the data is not defined until the first sck1 edge. the first sck1 edge shifts the first bit of data from the shifter onto the mosi1 output of the master and the miso1 output of the slave. the next sck1 edge causes both the master and slave to sample the data bit value on their miso1 and mosi1 inputs, respectively. at the third sck1 edge, the usi1 shifts the second data bit value out to the mosi1 and miso1 output of the master and slave respectively. when cpha1=1, the slave?s ss1 input is not required to go to its inactive high level between transfers. because the spi logic reuses the usi1 resources, spi mode of operation is similar to that of synchronous or asynchronous operation. an spi transfer is initiated by checking for the usi1 data register empty flag (dre1=1) and then writing a byte of data to the usi1dr register. in master mode of operation, even if transmission is not enabled (txe1=0), writing data to the usi1dr register is necessary because the clock sck1 is generated from transmitter block. sck1 (cpol1=1) miso1 mosi1 sck1 (cpol1=0) /ss0 out (master) bit7 bit0 /ss0 in (slave) bit6 bit1 ? ? bit2 bit5 bit0 bit7 bit1 bit6 sample msb first lsb first
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 236 11.13.13 usi1 spi block diagram rxcie1 rx control receive shift register (rxsr) data recovery dor1 checker usi1dr[0], (rx) tx control transmit shift register (txsr) usi1dr, (tx) i n t e r n a l b u s l i n e m u x loops 1 txc1 txcie1 drie1 dre1 empty signal to interrupt block int_ack clear rxc1 baud rate generator usi1bd txe1 sclk (fx: system clock) miso1 mosi1 m u x master1 d e p fxch1 sck1 sck control master1 rxe1 to interrupt block m u x edge detector and controller ss 1 ss control cpha1 cpol1 ord1 ( msb/lsb -1st) usi1dr[1], (rx) usi1 ssen figure 11.87 usi1 spi block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 237 11.13.14 usi1 i2c mode the usi1 can be set to operate in industrial standard serial communicatin protocols mode. the i2c mode uses 2 bus lines serial data line (sda1) and serial clock line (scl1) to exchange data. because both sda1 and scl1 lines are open-drain output, each line needs pull-up resistor. the features are as shown below. - compatible with i2c bus standard - multi-master operation - up to 400khz data transfer read speed - 7 bit address - both master and slave operation - bus busy detection 11.13.15 usi1 i2c bit transfer the data on the sda1 line must be stable during high period of the clock, scl1. the high or low state of the data line can only change when the clock signal on the scl1 line is low. the exceptions are start(s), repeated start(sr) and stop(p) condition where data line changes when clock line is high. figure 11.88 bit transfer on the i2c-bus (usi1) scl1 sda1 data line stable: data valid exept s, sr, p change of data allowed
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 238 11.13.16 usi1 i2c start / repeated start / stop one master can issue a start (s) condition to notice other devices connected to the scl1, sda1 lines that it will use the bus. a stop (p) condition is generated by the master to release the bus lines so that other devices can use it. a high to low transition on the sda1 line while scl1 is high defines a start (s) condition. a low to high transition on the sda1 line while scl1 is high defines a stop (p) condition. start and stop conditions are always generated by the master. the bus is considered to be busy after start condition. the bus is considered to be free again after stop condition, ie, the bus is busy between start and stop condition. if a repeated start condition (sr) is generated instead of stop condition, the bus stays busy. so, the start and repeated start conditions are functionally identical. figure 11.89 start and stop condition (usi1) 11.13.17 usi1 i2c data transfer every byte put on the sda1 line must be 8-bits long. the number of bytes that can be transmitted per transfer is unlimited. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. if a slave can?t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line scl1 low to force the master into a wait state. data transfer then continues when the slave is ready for another byte of data and releases clock line scl1. figure 11.90 data transfer on the i2c-bus (usi1) start or repeated start condition s or sr stop or repeated start condition sr or p msb a cknowledgement si g nal form slave a cknowledgement si g nal form slave byte complete, interru p t within device clock line held low while interru p ts are served. 1 9 1 9 ack ack sda1 scl1 sr p scl1 sda1 start condition s p stop condition
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 239 11.13.18 usi1 i2c acknowledge the acknowledge related clock pulse is generated by the master. the transmitter releases the sda1 line (high) during the acknowledge clock pulse. the receiver must pull down the sda1 line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. when a slave is addressed by a master (address packet), and if it is unable to receive or transmit because it?s performing some real time function, the data line must be left high by the slave. and also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must release the sda1 line (data packet). the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. if a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the slave transmitter must release the data line to allow the master to generate a stop or repeated start condition. figure 11.91 acknowledge on the i2c-bus (usi1) 11.13.19 usi1 i2c synchronization / arbitration clock synchronization is performed using the wired-and connection of i2c interfaces to the scl1 line. this means that a high to low transition on the scl1 line will cause the devices concerned to start counting off their low period and it will hold the scl1 line in that state until the clock high state is reached. however the low to high transition of this clock may not change the state of the scl1 line if another clock is still within its low period. in this way, a synchronized scl1 clock is generated with its low period determined by the device with the longest clock low period, and its high period determined by the one with the shortest clock high period. a master may start a transfer only if the bus is free. two or more masters may generate a start condition. arbitration takes place on the sda1 line, while the scl1 line is at the high level, in such a way that the master which transmits a high level, while another master is transmitting a low level will switch off its data output state because the level on the bus doesn?t correspond to its own level. arbitration continues for many bits until a winning master gets the ownership of i2c bus. its first stage is comparison of the address bits. 1 2 8 data output by transmitter 9 ack nack clock pulse for ack data output by receiver scl1 from master
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 240 figure 11.92 clock synchronization during arbitration procedure (usi1) figure 11.93 arbitration procedure of two masters (usi1) 11.13.20 usi1 i2c operation the i2c is byte-oriented and interrupt based. interrupts are issued after all bus events except for a transmission of a start condition. because the i2c is interrupt based, the application software is free to carry on other operations during a i2c byte transfer. note that when a i2c interrupt is generated, iic1ifr flag in usi1cr4 register is set, it is cleared by writing an any value to usi1st2. when i2c interrupt occurs, the scl1 line is hold low until writing any value to usi1st2. when the iic1ifr flag is set, the usi1st2 contains a value indicating the current state of the i2c bus. according to the value in usi1st2, software can decide what to do next. i2c can operate in 4 modes by configuring master/slave, transmitter/receiver. the operating mode is configured by a winning master. a more detailed explanation follows below. device1 dataout scl1 on bus device2 dataout sda1 on bus s arbitration process not ada p ed device 1 loses a rbitration device1 outputs high high counter reset fast device sclout slow device sclout scl1 wait high counting start high counting
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 241 11.13.20.1 usi1 i2c master transmitter to operate i2c in master transmitter, follow the recommended steps below. 10. enable i2c by setting usi1ms[1:0] bits in usi1cr1 and usi1en bit in usi1cr2. this provides main clock to the peripheral. 11. load sla1+w into the usi1dr where sla1 is address of slave device and w is transfer direction from the viewpoint of the master. for master transmitter, w is ?0?. note that usi1dr is used for both address and data. 12. configure baud rate by writing desired value to both usi1sclr and usi1schr for the low and high period of scl1 line. 13. configure the usi0sdhr to decide when sda1 changes value from falling edge of scl1. if sda1 should change in the middle of scl1 low period, load half the value of usi1sclr to the usi1sdhr. 14. set the startc1 bit in usi1cr4. this transmits a start condition. and also configure how to handle interrupt and ack signal. when the startc1 bit is set, 8-bit data in usi1dr is transmitted out according to the baud-rate. 15. this is ack sig nal processing stage for addr ess packet transmitted by ma ster. when 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or not in the 9 th high period of scl1. if the master gains bus mastership, i2c generates gcall interrupt regardless of the reception of ack from the slave device. when i2c loses bus mastership during arbitration process, the mlost1 bit in usi1st2 is set, and i2c waits in idle state or can be operate as an addressed slave. to operate as a slave when the mlost1 bit in usi1st2 is set, the ack1en bit in usi1cr4 must be set and the received 7-bit address must equal to the usi1sla[6:0] bits in usi1sar. in this case i2c operates as a slave transmitter or a slave receiver (go to appropriate section). in this stage, i2c holds the scl1 low. this is because to decide whether i2c continues serial transfer or stops communication. the following steps continue assuming that i2c does not lose mastership during first data transfer. i2c (master) can choose one of the following cases regardless of the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can receive more data from master. in this case, load data to transmit to usi1dr. 2) master stops data transfer even if it receives ack signal from slave. in this case, set the stopc1 bit in usi1cr4. 3) master transmits repeated start condition with not checking ack signal. in this case, load sla1+r/w into the usi1dr and set startc1 bit in usi1cr4. after doing one of the actions above, write any arbitrary to usi1st2 to release scl1 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi1dr and if transfer direction bit is ?1? go to master receiver section. 16. 1-byte of data is being transmitted. during data transfer, bus arbitration continues. 17. this is ack signal processing stage for data packet transmitted by master. i2c holds the scl1 low. when i2c loses bus mastership while transmitting data arbitrating other masters, the mlost1 bit in usi1st2 is set. if then, i2c waits in idle state. when the data in usi1dr is transmitted completely, i2c generates tend1 interrupt. i2c can choose one of the following cases regardless of the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can receive more data from master. in this case, load data to transmit to usi1dr. 2) master stops data transfer even if it receives ack signal from slave. in this case, set the stopc1 bit in usi1cr4. 3) master transmits repeated start condition with not checking ack signal. in this case, load sla1+r/w into the usi1dr and set the startc1 bit in usi1cr4. after doing one of the actions above, write any arbitrary to usi1st2 to release scl1 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi1dr, and if transfer di rection bit is ?1? go to master receiver section. 18. this is the final step for master transmitter function of i2c, handling stop interrupt. the stop bit indicates that data transfer between master and slave is over. to clear usi1st2, write any value to usi1st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 242 the next figure depicts above process for master transmitter operation of i2c. figure 11.94 formats and states in the master transmitter mode (usi1) from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl1 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& other master continues slave receiver (0x1d) or transmitter (0x1f) master receiver sla+w ack data rs stop lost lost& stop lost s or sr sla+r y n 0x0e 0x87 0x86 0x0e ack stop y n 0x0f 0x1d lost? y 0x47 0x1f 0x46 cont? y n stop 0x0f lost p 0x22 p 0x22 0x22 p
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 243 11.13.20.2 usi1 i2c master receiver to operate i2c in master receiver, follow the recommended steps below. 10. enable i2c by setting usi1ms[1:0] bits in usi1cr1 and usi1en bit in usi1cr2. this provides main clock to the peripheral. 11. load sla1+r into the usi1dr where sla is address of slave device and r is transfer direction from the viewpoint of the master. for master receiver, r is ?1?. note that usi1dr is used for both address and data. 12. configure baud rate by writing desired value to both usi1sclr and usi1schr for the low and high period of scl1 line. 13. configure the usi1sdhr to decide when sda1 changes value from falling edge of scl1. if sda1 should change in the middle of scl1 low period, load half the value of usi1sclr to the usi1sdhr. 14. set the startc1 bit in usi1cr4. this transmits a start condition. and also configure how to handle interrupt and ack signal. when the startc1 bit is set, 8-bit data in usi1dr is transmitted out according to the baud-rate. 15. this is ack sig nal processing stage for addr ess packet transmitted by ma ster. when 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave acknowledged or not in the 9 th high period of scl1. if the master gains bus mastership, i2c generates gcall interrupt regardless of the reception of ack from the slave device. when i2c loses bus mastership during arbitration process, the mlost1 bit in usi1st2 is set, and i2c waits in idle state or can be operate as an addressed slave. to operate as a slave when the mlost1 bit in usi1st2 is set, the ack1en bit in usi1cr4 must be set and the received 7-bit address must equal to the usi1sla[6:0] bits in usi1sar. in this case i2c operates as a slave transmitter or a slave receiver (go to appropriate section). in this stage, i2c holds the scl1 low. this is because to decide whether i2c continues serial transfer or stops communication. the following steps continue assuming that i2c does not lose mastership during first data transfer. i2c (master) can choose one of the following cases according to the reception of ack signal from slave. 1) master receives ack signal from slave, so continues data transfer because slave can prepare and transmit more data to master. configure ack0en bit in usi0cr4 to decide whether i2c acknowledges the next data to be received or not. 2) master stops data transfer because it receives no ack signal from slave. in this case, set the stopc1 bit in usi1cr4. 3) master transmits repeated start condition due to no ack signal from slave. in this case, load sla1+r/w into the usi1dr and set startc1 bit in usi1cr4. after doing one of the actions above, write arbitrary value to usi1st2 to release scl1 line. in case of 1), move to step 7. in case of 2), move to step 9 to handle stop interrupt. in case of 3), move to step 6 after transmitting the data in usi1dr and if transfer direction bit is ?0? go to master transmitter section. 16. 1-byte of data is being received. 17. this is ack signal processing stage for data packet transmitted by slave. i2c holds the scl1 low. when 1-byte of data is received completely, i2c generates tend1 interrupt. i2c can choose one of the following cases according to the rxack1 flag in usi1st2. 1) master continues receiving data from slave. to do this, set ack1en bit in usi0cr4 to acknowledge the next data to be received. 2) master wants to terminate data transfer when it receives next data by not generating ack signal. this can be done by clearing ack1en bit in usi1cr4. 3) because no ack signal is detected, master terminates data transfer. in this case, set the stopc1 bit in usi1cr4. 4) no ack signal is detected, and master transmits repeated start condition. in this case, load sla1+r/w into the usi1dr and set the startc1 bit in usi1cr4. after doing one of the actions above, write arbitrary value to usi1st2 to release scl1 line. in case of 1) and 2), move to step 7. in case of 3), move to step 9 to handle stop interrupt. in case of 4), move to step 6 after transmitting the data in usi1dr, and if transfer direction bit is ?0? go to master transmitter section.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 244 18. this is the final step for master receiver function of i2c, handling stop interrupt. the stop bit indicates that data transfer between master and slave is over. to clear usi1st2, write any value to usi1st2. after this, i2c enters idle state. the processes described above for master receiver operation of i2c can be depicted as th e followin g figure. figure 11.95 formats and states in the master receiver mode (usi1) from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl1 line is held low interrupt after stop command p ack arbitration lost as master and addressed as slave lost& other master continues slave receiver (0x1d) or transmitter (0x1f) master transmitter sla+r ack data rs lost lost& stop lost s or sr sla+w y n 0x0c 0x85 0x84 0x0c ack stop y n 0x0d 0x1d 0x45 0x1f 0x44 lost p 0x20 p 0x20 sr 0x44
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 245 11.13.20.3 usi1 i2c slave transmitter to operate i2c in slave transmitter, follow the recommended steps below. 8. if the main operating clock (sclk) of the system is slower than that of scl1, load value 0x00 into usi1sdhr to make sda1 change within one system clock period from the falling edge of scl1. note that the hold time of sda1 is calculated by sdah x period of sclk where sdah is multiple of number of sclk coming from usi1sdhr. wh en the hold time of sda1 is longe r than the period of sclk, i2c (slave) cannot transmit serial data properly. 9. enable i2c by setting usi1ms[1:0] bits in usi1cr1 , iic1ie bit in usi1cr4 and usi1en bit in usi1cr2. this provides main clock to the peripheral. 10. when a start condition is detected, i2c receives one byte of data and compares it with usi1sla[6:0] bits in usi1sar. if the gcall1 bit in usi1sar is enabled, i2c compares the received data with value 0x00, the general call address. 11. if the received address does not equal to usi1sla[6:0] bits in usi1sar, i2c enters idle state ie, waits for another start condition. else if the address equals to usi1sla[6:0] bits and the ack1en bit is enabled, i2c generates ssel1 interrupt and the scl1 line is held low. note that even if the address equals to usi1sla[6:0] bits, when the ack1en bit is disabled, i2c enters idle state. when ssel1 interrupt occurs, load transmit data to usi1dr and write arbitrary value to usi1st2 to release scl1 line. 12. 1-byte of data is being transmitted. 13. in this step, i2c generates tend1 interrupt and holds the scl1 line low regardless of the reception of ack signal from master. slave can select one of the following cases. 1) no ack signal is detected and i2c waits stop or repeated start condition. 2) ack signal from master is detected. load data to transmit into usi1dr. after doing one of the actions above, write arbitrary value to usi1st2 to release scl1 line. in case of 1) move to step 7 to terminate communication. in case of 2) move to step 5. in either case, a repeated start condition can be detected. for that case, move step 4. 14. this is the final step for slave transmitter function of i2c, handling stop interrupt. the stopc1 bit indicates that data transfer between master and slave is over. to clear usi1st2, write any value to usi1st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 246 the next figure shows flow chart for handling slave transmitter function of i2c. figure 11.96 formats and states in the slave transmitter mode (usi1) sla+r ack data lost& s or sr y 0x47 ack stop y n 0x46 p 0x22 idle idle y gcall 0x1f 0x97 0x17 from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl1 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 247 11.13.20.4 usi1 i2c slave receiver to operate i2c in slave receiver, follow the recommended steps below. 8. if the main operating clock (sclk) of the system is slower than that of scl1, load value 0x00 into usi1sdhr to make sda1 change within one system clock period from the falling edge of scl1. note that the hold time of sda1 is calculated by sdah x period of sclk where sdah is multiple of number of sclk coming from usi1sdhr. when the hold time of sda1 is long er than the period of sclk, i2c (slave) cannot transmit serial data properly. 9. enable i2c by setting usi1ms[1:0] bits in usi1cr1, iic1ie bit in usi1cr4 and usi1en bit in usi1cr2. this provides main clock to the peripheral. 10. when a start condition is detected, i2c receives one byte of data and compares it with usi1sla[6:0] bits in usi1sar. if the gcall1 bit in usi1sar is enabled, i2c1 compares the received data with value 0x00, the general call address. 11. if the received address does not equal to sla1 bits in usi1sar, i2c enters idle state ie, waits for another start condition. else if the address equals to sla1 bits and the ack1en bit is enabled, i2c generates ssel1 interrupt and the scl1 line is held low. note that even if the address equals to sla1 bits, when the ack1en bit is disabled, i2c enters idle state. when ssel1 interrupt occurs and i2c is ready to receive data, write arbitrary value to usi1st2 to release scl1 line. 12. 1-byte of data is being received. 13. in this step, i2c generates tend1 interrupt and holds the scl1 line low regardless of the reception of ack signal from master. slave can select one of the following cases. 1) no ack signal is detected (ack1en=0) and i2c waits stop or repeated start condition. 2) ack signal is detected (ack1en=1) and i2c can continue to receive data from master. after doing one of the actions above, write arbitrary value to usi1st2 to release scl1 line. in case of 1) move to step 7 to terminate communication. in case of 2) move to step 5. in either case, a repeated start condition can be detected. for that case, move step 4. 14. this is the final step for slave receiver function of i2c, handling stop interrupt. the stopc1 bit indicates that data transfer between master and slave is over. to clear usi1st2, write any value to usi1st2. after this, i2c enters idle state.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 248 the process can be depicted as following figure when i2c operat es in slave re ceiver mode. figure 11.97 formats and states in the slave receiver mode (usi1) sla+w ack data lost& s or sr y n 0x45 ack stop y n 0x44 p 0x20 idle idle y gcall 0x1d 0x95 0x15 from master to slave / master command or data write from slave to master 0xxx value of status register ack interrupt , scl1 line is held low interrupt after stop command p arbitration lost as master and addressed as slave lost& general call address gcall
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 249 11.13.21 usi1 i2c block diagram receive shift register (rxsr) transmit shift register (txsr) i n t e r n a l b u s l i n e sclk (fx: system clock) sda1 scl1 usi1dr, (rx) vss n-ch vss n-ch scl1 out controller sda1 in/out controller sda hold time register usi1sdhr scl low period register usi1sclr scl high period register usi1schr time generator and time controller usi1dr, (tx) slave address register usi1sar general call and address detector usi1gce stop /start condition generator stopc1 startc1 ack signal generator ack1en rxack1, gcall 1, tend1, stopd1, ssel 1, mlost1, busy1, tmode1 interrupt generator to interrupt block iic1ifr iic1ie note) when the usi1 block is an i2c mode and the corresponding port is an sub-function for scl1/sda1 pin, the scl1/sda1 pins are automatically set to the n-channel open-drain outputs and the input latch is read in the case of reading the pins. the corresponding pull-up resistor is determined by the control register. figure 11.98 usi1 i2c block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 250 11.13.22 register map table 11-24 usi1 register map name address dir default description usi1bd f3h r/w ffh usi1 baud rate generation register usi1dr f5h r/w 00h usi1 data register usi1sdhr f4h r/w 01h usi1 sda hold time register usi1schr f7h r/w 3fh usi1 scl high period register usi1sclr f6h r/w 3fh usi1 scl low period register usi1sar edh r/w 00h usi1 slave address register usi1cr1 e9h r/w 00h usi1 control register 1 usi1cr2 eah r/w 00h usi1 control register 2 usi1cr3 ebh r/w 00h usi1 control register 3 usi1cr4 ech r/w 00h usi1 control register 4 usi1st1 f1h r/w 80h usi1 status register 1 usi1st2 f2h r 00h usi1 status register 2 11.13.23 usi1 register description usi1 module consists of usi1 baud rate generation register (usi1bd), usi1 data register (usi1dr), usi1 sda hold time register (usi1sdhr), usi1 scl high period register (usi1schr), usi1 scl low period register (usi1sclr), usi1 slave address register (usi1sar), usi1 control register 1/2/3/4 (usi1cr1/2/3/4), usi1 status register 1/2 (usi1st1/2). 11.13.24 register description for usi1 usi1bd (usi1 baud- rate generation register: for uart and spi mode) : f3h 7 6 5 4 3 2 1 0 usi1bd7 usi1bd 6 usi1bd 5 usi1bd 4 usi1bd 3 usi1bd 2 usi1bd 1 usi1bd 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : ffh usi1bd[7:0] the value in this register is used to generate internal baud rate in asynchronous mode or to generate sck1 clock in spi mode. to prevent malfunction, do not write ?0? in asynchronous mode and do not write ?0? or ?1? in spi mode. note) in common with usi1sar register, usi1bd register is used for slave address register when the usi1 i2c mode.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 251 usi1dr (usi1 data register: for uart, spi, and i2c mode) : f5h 7 6 5 4 3 2 1 0 usi1dr7 usi1dr 6 usi1dr 5 usi1dr 4 usi1dr 3 usi1dr 2 usi1dr 1 usi1dr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1dr[7:0] the usi1 transmit buffer and receive buffer share the same i/o address with this data register. the transmit data buffer is the destination for data written to the usi1dr register. reading the usi1dr register returns the contents of the receive buffer. write to this register only when the dre1 flag is set. in spi master mode, the sck1 clock is generated when data are written to this register. usi1sdhr (usi1 sda hold time register: for i2c mode) : f4h 7 6 5 4 3 2 1 0 usi1sdhr7 usi1sdhr6 usi1sdhr5 usi1sdhr 4 usi1sdhr 3 usi1sdhr 2 usi1sdhr 1 usi1sdhr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1sdhr[7:0] the register is used to control sda1 output timing from the falling edge of scl1 in i2c mode. note) that sda1 is changed after t sclk x (usi1sdhr+2), in master sda1 change in the middle of scl1. in slave mode, configure this register regarding the frequency of scl1 from master. the sda1 is changed after tscl k x (usi1sdhr+2) in master mode. so, to insure operation in slave mode, the value t sclk x (usi1sdhr +2) must be smalle r than the period of scl1. usi1schr (usi1 scl high period register: for i2c mode) : f7h 7 6 5 4 3 2 1 0 usi1schr7 usi1schr6 usi1schr5 usi1schr 4 usi1schr 3 usi1schr 2 usi1schr 1 usi1schr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1schr[7:0] this register defines the high period of scl1 when it operates in i2c master mode. the base clock is sclk, the system clock, and the period is calculated by the formula: t sclk x (4 x usi1schr +2) where t sclk is the period of sclk. so, the operating frequency of i2c master mode is calculated by the following equation. f i2c = t sclk x ( 4 x ( usi1sclr + usi1schr + 4 )) 1
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 252 usi1sclr (usi1 scl low period register: for i2c mode) : f6h 7 6 5 4 3 2 1 0 usi1sclr7 usi1sclr6 usi1sclr5 usi1sclr 4 usi1sclr 3 usi1sclr 2 usi1sclr 1 usi1sclr 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1sclr[7:0] this register defines the high period of scl1 when it operates in i2c master mode. the base clock is sclk, the system clock, and the period is calculated by the formula: t sclk x (4 x usi1sclr +2) where t sclk is the period of sclk. usi1sar (usi1 slave address register: for i2c mode) : edh 7 6 5 4 3 2 1 0 usi1sla6 usi1sla5 usi1sla4 usi1sla3 usi1sla2 usi1sla1 usi1sla0 usi1gce r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1sla[6:0] these bits configure the slave address of i2c when it operaties in i2c slave mode. upm[1:0] this bit decides whether i2c allows general call address or not in i2c slave mode. 0 ignore general call address 1 allow general call address
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 253 usi1cr1 (usi1 control register 1: for uart, spi, and i2c mode) : e9h 7 6 5 4 3 2 1 0 usi1ms1 usi1ms0 usi1pm1 usi1pm0 usi1s2 usi1s1 ord1 usi1s0 cpha1 cpol1 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h usi1ms[1:0] selects operation mode of usi1 usi1ms1 usi1ms0 operation mode 0 0 asynchronous mode (uart) 0 1 synchronous mode 1 0 i2c mode 1 1 spi mode usi1pm[1:0] selects parity generation and check methods (only uart mode) usi1pm1 usi1pm0 parity 0 0 no parity 0 1 reserved 1 0 even parity 1 1 odd parity usi1s[2:0] when in asynchronous or synchronous mode of operation, selects the length of data bits in frame usi1s2 usi1s1 usi1s0 data length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 9 bit ord1 this bit in the same bit position with usi1s1. the msb of the data byte is transmitted first when set to ?1? and the lsb when set to ?0? (onl spi mode) 0 lsb-first 1 msb-first cpol1 this bit determines the clock polarity of ack in synchronous or spi mode. 0 txd change@rising edge, rxd change@falling edge 1 txd change@falling edge, rxd change@rising edge cpha1 this bit is in the same bit position with usi1s0. this bit determines if data are sampled on the leading or trailing edge of sck1 (only spi mode). cpol1 cpha1 l eading edge trailing edge 0 0 sample (rising) setup (falling) 0 1 setup (rising) sample (falling) 1 0 sample (falling) setup (rising) 1 1 setup (falling) sample (rising)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 254 usi1cr2 (usi1 control register 2: for uart, spi, and i2c mode) : eah 7 6 5 4 3 2 1 0 drie1 txcie1 rxcie1 wakeie1 txe1 rxe1 usi1en dbls1 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h drie1 interrupt enable bit for data register empty (only uart and spi mode). 0 interrupt from dre1 is inhibited (use polling) 1 when dre1 is set, request an interrupt txcie1 interrupt enable bit for transmit complete (only uart and spi mode). 0 interrupt from txc1 is inhibited (use polling) 1 when txc1 is set, request an interrupt rxcie1 interrupt enable bit for receive complete (only uart and spi mode). 0 interrupt from rxc1 is inhibited (use polling) 1 when rxc1 is set, request an interrupt wakeie1 interrupt enable bit for asynchronous wake in stop mode. when device is in stop mode, if rxd1 goes to low level an interrupt can be requested to wake-up system. (only uart mode). at that time the drie1 bit and usi1st1 register value should be set to ?0b? and ?00h?, respectively. 0 interrupt from wake is inhibited 1 when wake1 is set, request an interrupt txe1 enables the transmitter unit (only uart and spi mode). 0 transmitter is disabled 1 transmitter is enabled rxe1 enables the receiver unit (only uart and spi mode). 0 receiver is disabled 1 receiver is enabled usi1en activate usi1 function block by supplying. 0 usi1 is disabled 1 usi1 is enabled dbls1 this bit selects receiver sampling rate (only uart) 0 normal asynchronous operation 1 double speed asynchronous operation
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 255 usi1cr3 (usi1 control register 3: for uart, spi, and i2c mode) : ebh 7 6 5 4 3 2 1 0 master1 loops1 dissck1 usi1ssen fxch1 usi1sb usi1tx8 usi1rx8 r/w r/w r/w r/w r/w r/w r/w r initial value : 00h master1 selects master or slave in spi and synchronous mode operation and controls the direction of sck1 pin 0 slave mode operation (external clock for sck1). 1 master mode operation(internal clock for sck1). loops1 controls the loop back mode of usi1 for test mode (only uart and spi mode) 0 normal operation 1 loop back mode dissck1 in synchronous mode of operation, selects the waveform of sck1 output 0 ack is free-running while uart is enabled in synchronous master mode 1 ack is active while any frame is on transferring usi1ssen this bit controls the ss1 pin operation (only spi mode) 0 disable 1 enable (the ss1 pin should be a normal input) fxch1 spi port function exchange control bit (only spi mode) 0 no effect 1 exchange mosi1 and miso1 function usi1sb selects the length of stop bit in asynchronous or synchronous mode of operation. 0 1 stop bit 1 2 stop bit usi1tx8 the ninth bit of data frame in as ynchronous or synchronous mode of operation. write this bit first before loading the usi1dr register 0 msb (9 th bit) to be transmitted is ?0? 1 msb (9 th bit) to be transmitted is ?1? usi1rx8 the ninth bit of data frame in as ynchronous or synchronous mode of operation. read this bit first before reading the receive buffer (only uart mode). 0 msb (9 th bit) received is ?0? 1 msb (9 th bit) received is ?1?
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 256 usi1cr4 (usi1 control register 4: for i2c mode) : ech 7 6 5 4 3 2 1 0 iic1ifr ? txdlyenb1 iic1ie ack1en imaster1 stopc1 startc1 r ? r/w r/w r/w r r/w r/w initial value : 00h iic1ifr this is an interrupt flag bit for i2c mode. when an interrupt occurs, this bit becomes ?1?. this bit is cleared when write any values in th usi1st2. 0 i2c interrupt no generation 1 i2c interrupt generation txdlyenb1 usi1sdhr register control bit 0 enable usi1sdhr register 1 disable usi1sdhr register iic1ie interrupt enable bit for i2c mode 0 interrupt from i2c is inhibited (use polling) 1 enable interrupt for i2c ack1en controls ack signal generation at ninth scl1 period. 0 no ack signal is generated (sda1 =1) 1 ack signal is generated (sda1 =0) notes) ack signal is output (sda1 =0) for the following 3 cases. 1. when received address packet equals to usi1sla bits in usi1sar. 2. when received address packet equals to value 0x00 with gcall1 enabled. 3. when i2c operates as a receiver (master or slave) imaster1 represent operating mode of i2c 0 i2c is in slave mode 1 i2c is in master mode stopc1 when i2c is master, stop condition generation 0 no effect 1 stop condition is to be generated startc1 when i2c is master, start condition generation 0 no effect 1 start or repeated start condition is to be generated
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 257 usi1st1 (usi1 status register 1: for uart and spi mode) : f1h 7 6 5 4 3 2 1 0 dre1 txc1 rxc1 wake1 usi1rst dor1 fe1 pe1 r/w r/w r r/w r/w r r/w r/w initial value : 80h dre1 the dre1 flag indicates if the transmit buffer (usi1dr) is ready to receive new data. if dre1 is ?1?, the buffer is empty and ready to be written. this flag can generate a dre1 interrupt. 0 transmit buffer is not empty. 1 transmit buffer is empty. txc1 this flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. this flag is automatically cleared when the interrupt service routine of a txc1 interrupt is executed. this flag can generate a txc1 interrupt. this bit is automatically cleared. 0 transmission is ongoing. 1 transmit buffer is empty and the data in transmit shift register are shifted out completely. rxc1 this flag is set when there are unread data in the receive buffer and cleared when all the data in the receive buffer are read. the rxc1 flag can be used to generate a rxc1 interrupt. 0 there is no data unread in the receive buffer 1 there are more than 1 data in the receive buffer wake1 this flag is set when the rxd1 pin is detected low while the cpu is in stop mode. this flag can be used to generat e a wake1 interrupt. this bit is set only when in asynchronous mode of operation. this bit should be cleared by program software. (only uart mode) 0 no wake interrupt is generated. 1 wake interrupt is generated usi1rst this is an internal reset and only has effect on usi1. writing ?1? to this bit initializes the internal logic of usi1 and this bit is automatically cleared to ?0?. 0 no operation 1 reset usi1 dor1 this bit is set if a data overrun occurs. while this bit is set, the incoming data frame is ignored. this flag is valid until the receive buffer is read. 0 no data overrun 1 data overrun detected fe1 this bit is set if the first stop bit of next character in the receive buffer is detected as ?0?. this bit is valid until the receive buffer is read. (only uart mode) 0 no frame error 1 frame error detected pe1 this bit is set if the next character in the receive buffer has a parity error to be received while parity checking is enabled. this bit is valid until the receive buffer is read. (only uart mode) 0 no parity error 1 parity error detected
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 258 usi1st2 (usi1 status register 2: for i2c mode) : f2h 7 6 5 4 3 2 1 0 gcall1 tend1 stopd1 ssel1 mlost1 busy1 tmode1 rxack1 r r/w r/w r/w r/w r/w r/w r/w initial value : 00h gcall1 (note) this bit has different meaning depending on whether i2c is master or slave. when i2c is a master, this bit represents whether it received aack (address ack) from slave. 0 no aack is received (master mode) 1 aack is received (master mode) when i2c is a slave, this bit is used to indicated general call. 0 general call address is not detected (slave mode) 1 general call address is detected (slave mode) tend1 (note) this bit is set when 1-byte of data is transferred completely 0 1 byte of data is not completely transferred 1 1 byte of data is completely transferred stopd1 (note) this bit is set when a stop condition is detected. 0 no stop condition is detected 1 stop condition is detected ssel1 (note) this bit is set when i2c is addressed by other master. 0 i2c is not selected as a slave 1 i2c is addressed by other master and acts as a slave mlost1 (note) this bit represents the result of bus arbitration in master mode. 0 i2c maintains bus mastership 1 i2c maintains bus mastership during arbitration process busy1 this bit reflects bus status. 0 i2c bus is idle, so a master can issue a start condition 1 i2c bus is busy tmode1 this bit is used to indicate whether i2c is transmitter or receiver. 0 i2c is a receiver 1 i2c is a transmitter rxack1 this bit shows the state of ack signal 0 no ack is received 1 ack is received at ninth scl period note) these bits can be source of interrupt. when an i2c interrupt occurs except for stop mode, the scl1 line is hold low. to release scl1, write rbitrary value to usi1st2. when usi1st2 is written, the tend1, stopd1, ssel1, mlost1, and rxack1 bits are cleared.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 259 11.14.1 baud rate setting (example) table 11-25 examples of usi0bd and usi1bd settings for commonly used oscillator frequencies baud rate fx=1.00mhz fx=1.8432mhz fx=2.00mhz usi0bd/usi1bd error usi0bd/usi1bd error usi0bd/usi1bd error 2400 25 0.2% 47 0.0% 51 0.2% 4800 12 0.2% 23 0.0% 25 0.2% 9600 6 -7.0% 11 0.0% 12 0.2% 14.4k 3 8.5% 7 0.0% 8 -3.5% 19.2k 2 8.5% 5 0.0% 6 -7.0% 28.8k 1 8.5% 3 0.0% 3 8.5% 38.4k 1 -18.6% 2 0.0% 2 8.5% 57.6k - - 1 -25.0% 1 8.5% 76.8k - - 1 0.0% 1 -18.6% 115.2k - - - - - - 230.4k - - - - - - (continued) baud rate fx=3.6864mhz fx=4.00mhz fx=7.3728mhz usi0bd/usi1bd error usi0bd/usi1bd error usi0bd/usi1bd error 2400 95 0.0% 103 0.2% 191 0.0% 4800 47 0.0% 51 0.2% 95 0.0% 9600 23 0.0% 25 0.2% 47 0.0% 14.4k 15 0.0% 16 2.1% 31 0.0% 19.2k 11 0.0% 12 0.2% 23 0.0% 28.8k 7 0.0% 8 -3.5% 15 0.0% 38.4k 5 0.0% 6 -7.0% 11 0.0% 57.6k 3 0.0% 3 8.5% 7 0.0% 76.8k 2 0.0% 2 8.5% 5 0.0% 115.2k 1 0.0% 1 8.5% 3 0.0% 230.4k - - - - 1 0.0% 250k - - - - 1 -7.8% 0.5m - - - - - - (continued) baud rate fx=8.00mhz fx=11.0592mhz usi0bd/usi1bd error usi0bd/usi1bd error 2400 207 0.2% - - 4800 103 0.2% 143 0.0% 9600 51 0.2% 71 0.0% 14.4k 34 -0.8% 47 0.0% 19.2k 25 0.2% 35 0.0% 28.8k 16 2.1% 23 0.0% 38.4k 12 0.2% 17 0.0% 57.6k 8 -3.5% 11 0.0% 76.8k 6 -7.0% 8 0.0% 115.2k 3 8.5% 5 0.0% 230.4k 1 8.5% 2 0.0% 250k 1 0.0% 2 -7.8% 0.5m - - - - 1m - - - -
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 260 11.15 lcd driver 11.15.1 overview the lcd driver is controlled by the lcd control register (lcdcrh/l). the lclk[1:0] determines the frequency of com sign al scanning of each segment output. a reset clears the lcd control register lcdcrh and lcdcrl values to logic ?0?. the lcd display can continue operating during idle and stop modes if a sub-frequency clock is used as system clock source.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 261 11.15.2 lcd display ram organization display data are stored to the display data area in the external data memory. the display data which stored to the display external data area (address 0000h-001ah) are read automatically and sent to the lcd driver by the hardware. the lcd driver generates the segment signals and common signals in accordance with the display data and drive method. therefore, display patterns can be changed by only overwriting the contents of the display external data area with a program. figure 11-99 shows the correspondence between the display external data area and the com/seg pins. the lcd is turned on when the display data is ?1? and turned off when ?0?. seg 26 001 ah seg 25 0019 h seg 24 seg 23 seg 22 0016 h seg 7 0007 h seg 6 0006 h seg 5 0005 h seg 4 0004 h seg 3 0003 h seg 2 0002 h seg 1 0001 h seg 0 0000 h bit0 bit1 bit2 bit3 c o m 0 bit4 bit5 bit6 bit7 0017 h 0018 h c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 figure 11.99 lcd circuit block diagram
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 262 11.15.3 lcd signal waveform 1 frame vdd vss 01 com1 seg1 com0-seg0 com0 vss vlc0 vlc2(vlc1, vlc3) com0 com1 seg0 seg1 seg3 01 seg2 seg0 vss vss +vlc0 +vlc2(vlc1, vlc3) -vlc2(vlc1, vlc3) -vlc0 vss vss vlc0 vlc2(vlc1, vlc3) vlc0 vlc2(vlc1, vlc3) vlc0 vlc2(vlc1, vlc3) figure 11.100 lcd signal waveforms (1/2duty, 1/2bias)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 263 com1 com0 seg3 seg1 seg2 com2 1 frame vdd vss 01 com1 seg2 com0-seg1 com0 vlc2(vlc3) vlc0 vlc1 seg1 +vlc2(vlc3) +vlc0 +vlc1 vss -vlc2(vlc3) 2 01 2 vss vlc2(vlc3) vlc0 vlc1 vss com2 vlc2(vlc3) vlc0 vlc1 vss vlc2(vlc3) vlc0 vlc1 vss vlc2(vlc3) vlc0 vlc1 vss -vlc0 -vlc1 figure 11.101 lcd signal waveforms (1/3duty, 1/3bias)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 264 com1 com0 seg3 seg2 com3 com2 1 frame vdd vss 01 com1 seg3 com0-seg2 com0 vlc2(vlc3) vlc0 vlc1 seg2 +vlc2(vlc3) +vlc0 +vlc1 vss -vlc2(vlc3) 2 vss vlc2(vlc3) vlc0 vlc1 vss com2 vlc2(vlc3) vlc0 vlc1 vss vlc2(vlc3) vlc0 vlc1 vss vlc2(vlc3) vlc0 vlc1 vss -vlc0 -vlc1 3 01 2 3 figure 11.102 lcd signal waveforms (1/4duty, 1/3bias)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 265 com0 com1 com2 com3 com4 com5 com6 com7 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 1 frame vdd vss 0 com1 seg7 com0-seg6 com0 vlc2 vlc0 vlc1 seg6 vss com2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 vlc3 vlc2 vlc0 vlc1 vss vlc3 vlc2 vlc0 vlc1 vss vlc3 vlc2 vlc0 vlc1 vss vlc3 vlc2 vlc0 vlc1 vss vlc3 +vlc2 +vlc0 +vlc1 vss +vlc3 -vlc1 -vlc3 -vlc2 -vlc0 figure 11.103 lcd signal waveforms (1/8duty, 1/4bias)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 266 11.15.4 lcd voltage dividing resistor connection vss rrrr vlc0 vlc1 vlc2 vlc3 vlcd (1/ 4 bias) vlc0 vlc1 vlc2 vlc3 vss rr vlc0 vlc1 vlc2 vlc3 vlcd (1/2 bias, 160 k ohm) vlc0 vlc1 vlc2 vlc3 rr vss rr vlc0 vlc1 vlc2 vlc3 vlcd (1/ 2 bias, 80 k ohm ) vlc0 vlc1 vlc2 vlc3 lcten disp vss r vlc0 vlc1 vlc2 vlc3 vlcd (1/ 3 bias) vlc0 vlc1 vlc2 vlc3 r co ntr a st co ntr oller lcten disp co nt ra s t controller lcten disp contrast cont ro lle r lcten disp contrast controller r notes) 1. the above figures are for the internal resistor bias connection. so, it is not needed an external connection. 2. when the internal resistors are selected, all the p40/vlc3, p41/vlc2, p42/vlc1 and p43/vlc0 pins can be used for normal i/o. figure 11.104 internal resistor bias connection
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 267 vss r r r r vlc0 vlc1 vlc2 vlc3 vlcd (1/ 4 bias) vss r r vlc0 vlc1 vlc2 vlc3 vlcd (1/ 2 bias) vss r r r vlc0 vlc1 vlc2 vlc3 vlcd (1/ 3 bias) lcten disp contrast controller lcten disp contrast controller lcten disp contrast controller notes) 1. when the external resistor bias is selected, the internal resistors for bias are disconnected. 2. when the external resistor bias is selected, the dividing resistors should be connected like the above figure and the needed bias pins should be selected as the lcd bias function pins (vlc0, vlc1, vlc2, and vlc3) by p4fsr register. - when it is 1/2 bias, the p43/vlc0 and p41/vlc2 pins should be selected as vlc0 and vlc2 functions. the other pins can be used for normal i/o. - when it is 1/3 bias, the p43/vlc0, p42/vlc1, and p41/vlc2 pins should be selected as vlc0, vlc1, and vlc2 functions. another pin can be used for normal i/o. - when it is 1/4 bias, the p43/vlc0, p42/vlc1, p41/vlc2, and p40/vlc3 pins should be selected as vlc0, vlc1, vlc2, and vlc3 functions figure 11.105 external resistor bias connection
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 268 11.15.5 block diagram port latch flcd lcd display ram lcdcrl lcdcrh timing controller lcd bias voltage generator com/port driver seg/port driver vlc2 vlc1 vlc0 vlc3 lcdccr contrast controller figure 11.106 lcd circuit block diagram 11.15.6 register map table 11-26 lcd register map name address dir default description lcdcrh 9ah r/w 00h lcd driver control high register lcdcrl 99h r/w 00h lcd driv er control low register lcdccr 9bh r/w 00h lcd contrast control register 11.15.7 lcd driver register description lcd driver register has two control registers, lcd driver control high register (lcdcrh), lcd driver control low register (lcdcrl) and lcd contrast control register.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 269 11.15.8 register description for lcd driver lcdcrh (lcd driver control high register) : 9ah 7 6 5 4 3 2 1 0 ? ? ? comchg ? ? lcddr disp ? ? ? r/w ? ? r/w r/w initial value : 00h comchg common signal output port change control 0 com0 ? com3 signals are outputted through the p37-p34 1 com0 ? com3 signals are outputted through the p33-p30 notes) 1. the com0/com1/com2/com3 signals can be outputted through the p33/p32/p31/p30, respectively. 2. for example, the com0 signal may be outputted to p33 pin if the p3fsr.3 is ?1b? and the comchg bit is ?1b?. 3. refer to the port3 function selection register (p3fsr). 4. available only below the 1/4 duty. lcddr lcd driving resistor for bias select 0 internal lcd driving resistors for bias 1 external lcd driving resistors for bias disp lcd display control 0 display off 1 normal display on
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 270 lcdcrl (lcd driver control low register) : 99h 7 6 5 4 3 2 1 0 ? ? dbs3 dbs2 dbs1 dbs0 lclk1 lck0 ? ? r./w r/w r/w r/w r/w r/w initial value : 00h dbs[3:0] lcd duty and bias select (note) dbs3 dbs2 dbs1 dbs0 description 0 0 0 0 1/8duty, 1/4bias (60k ohm) 0 0 0 1 1/6duty, 1/4bias (60k ohm) 0 0 1 0 1/5duty, 1/3bias (60k ohm) 0 0 1 1 1/4duty, 1/3bias (60k ohm) 0 1 0 0 1/3duty, 1/3bias (60k ohm) 0 1 0 1 1/3duty, 1/2bias (60k ohm) 0 1 1 0 1/3duty, 1/2bias (120k ohm) 0 1 1 1 1/2duty, 1/2bias (60k ohm) 1 0 0 0 1/2duty, 1/2bias (120k ohm) other values not available lclk[1:0] lcd clock select (when f wck (watch timer clock)= 32.768 khz) lclk1 lclk0 description 0 0 f lcd = 128hz 0 1 f lcd = 256hz 1 0 f lcd = 512hz 1 1 f lcd = 1024hz note) the lcd clock is generated by watch timer clock (f wck ). so the watch timer should be enabled when the lcd display is turned on.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 271 lcdccr (lcd driver contrast control low register) : 9bh 7 6 5 4 3 2 1 0 lcten ? ? ? vlcd3 vlcd vlcd1 vlcd0 r/w ? ? ? r/w r/w r/w r/w initial value : 00h lcten control lcd driver contrast 0 lcd driver contrast disable 1 lcd driver contrast enable vlcd[3:0] vlc0 voltage control when the contrast is enabled vlcd3 vlcd 2 vlcd 1 vlcd 0 description 0 0 0 0 vlc0 = vdd x 16/31 step 0 0 0 1 vlc0 = vdd x 16/30 step 0 0 1 0 vlc0 = vdd x 16/29 step 0 0 1 1 vlc0 = vdd x 16/28 step 0 1 0 0 vlc0 = vdd x 16/27 step 0 1 0 1 vlc0 = vdd x 16/26 step 0 1 1 0 vlc0 = vdd x 16/25 step 0 1 1 1 vlc0 = vdd x 16/24 step 1 0 0 0 vlc0 = vdd x 16/23 step 1 0 0 1 vlc0 = vdd x 16/22 step 1 0 1 0 vlc0 = vdd x 16/21 step 1 0 1 1 vlc0 = vdd x 16/20 step 1 1 0 0 vlc0 = vdd x 16/19 step 1 1 0 1 vlc0 = vdd x 16/18 step 1 1 1 0 vlc0 = vdd x 16/17 step 1 1 1 1 vlc0 = vdd x 16/16 step notes) the lcd contrast step is based on 1/4 bias. 1/4 bias : vdd x (16/31 ? vlc[3:0]) 1/3 bias : vdd x (12/27 ? vlc[3:0]) 1/2 bias : vdd x (8/23 ? vlc[3:0])
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 272 12. power down operation 12.1 overview the z51f3220 has two power-down modes to minimize the power consumption of the device. in power down mode, power consumption is reduced considerably. the device provides three kinds of power saving functions, main-idle, sub-idle and stop mode. in three modes, program is stopped. 12.2 peripheral operation in idle/stop mode table 12-1 peripheral operation during power down mode peripheral idle mode stop mode cpu all cpu operation are disable all cpu operation are disable ram retain retain basic interval timer operates continuously stop watch dog timer operates continuously stop (can be operated with wdtrc osc) watch timer operates continuously stop (can be operated with sub clock) timer0~4 operates continuously halted (only when the event counter mode is enabled, timer operates normally) adc operates continuously stop buz operates continuously stop spi operates continuously only operate with external clock usi0/1 operates continuously only operate with external clock lcd controller operates continuously stop (can be operated with sub clock) internal osc (16mhz) oscillation stop when the system clock (fx) is f irc wdtrc osc (5khz) stop can be operated with setting value main osc (0.4~12mhz) oscillation stop when fx = f xin sub osc (32.768khz) oscillation stop when fx = f sub i/o port retain retain control register retain retain address data bus retain retain release method by reset, all interrupts by reset, timer interrupt (ec0, ec1, ec3), spi (external clock), external interrupt, uart by ack, wt (sub clock), wdt
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 273 12.3 idle mode the power control register is set to ?01h? to enter the idle mode. in this mode, the internal oscillation circuits remain active. oscillation continues and peripherals are operated normally but cpu stops. it is released by reset or interrupt. to be released by interrupt, interrupt should be enabled before idle mode. if using reset, because the device becomes initialized state, the registers have reset value. figure 12.1 idle mode release timing by external interrupt external interrupt osc normal operation release cpu clock stand-by mode normal operation
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 274 12.4 stop mode the power control register is set to ?03h? to enter the stop mode. in the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. for example, if the internal rc oscillator (f irc ) is selected for the system clock and the sub clock (f sub ) is oscillated, the internal rc oscillator stops oscillation and the sub clock is continuously oscillated in stop mode. at that time, the watch timer and lcd controller can be operated with the sub clock. the source for exit from stop mode is hardware reset and interrupts. the reset re-defines all the control registers. when exit from stop mode, enough oscillation stabilization time is required to normal operation. figure 12.2 shows the timing diagram. when released from stop mode, the basic interval timer is activated on wake-up. therefore, before stop instruction, user must be set its relevant prescale divide ratio to have long enough time. this guarantees that oscillator has started and stabilized. figure 12.2 stop mode release timing by external interrupt osc cpu clock external interrupt normal operation bit counter stop operation normal operation release stop instruction execute clear & start by software setting before executed stop instruction, bit must be set properly by software to get stabilization. n n+1 n+2 n+3 ff 0 1 1 2 fe 0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 275 12.5 release operation of stop mode after stop mode is released, the operation begins according to content of related interrupt register just before stop mode start (figure 12.3). if the global interrupt enable flag (ie.ea) is set to `1`, the stop mode is released by the interrupt which each interrupt enable flag = `1` and the cpu jumps to the relevant interrupt service routine. even if the ie.ea bit is cleared to ?0?, the stop mode is released by the interrupt of which the interrupt enable flag is set to ?1?. figure 12.3 stop mode release flow set pcon[7:0] set iex.b stop mode iex.b==1 ? interrupt request stop mode release y interrupt service routine next instruction n corresponding interrupt enable bit(ie, ie1, ie2, ie3)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 276 12.5.1 register map table 12-2 power down operation register map name address dir default description pcon 87h r/w 00h power control register 12.5.2 power down operation register description the power down operation register consists of the power control register (pcon). 12.5.3 register description for power down operation pcon (power control register) : 87h 7 6 5 4 3 2 1 0 pcon7 ? ? ? pcon3 pcon2 pcon1 pcon0 r/w ? ? ? r/w r/w r/w r/w initial value : 00h pcon[7:0] power control 01h idle mode enable 03h stop mode enable other values normal operation notes) 1. to enter idle mode, pcon must be set to ?01h?. 2. to enter stop mode, pcon must be set to ?03h?. 3. the pcon register is automatically cleared by a release signal in stop/idle mode. 4. three or more nop instructions must immediately follow the instruction that make the device enter stop/idle mode. refer to the following examples. ex1) mov pcon, #01h ; idle mode ex2) mov pcon, #03h ; stop mode nop nop nop nop nop nop ? ? ? ? ? ?
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 277 13. reset 13.1 overview the following is the hardware setting value. table 13-1 reset state on chip hardware initial value program counter (pc) 0000h accumulator 00h stack pointer (sp) 07h peripheral clock on control register refer to the peripheral registers 13.2 reset source the z51f3220 has five types of reset sources. the following is the reset sources. - external resetb - power on reset (por) - wdt overflow reset (in the case of wdten = `1`) - low voltage reset (in the case of lvren = `0 `) - ocd reset 13.3 reset block diagram figure 13.1 reset block diagram wdt rst wdt rsten ext reset disable by fuse reset noise canceller lvr lvr enable reset noise canceller por rst ocd rst s q r internal reset ifbit (bit overflow) ocd rsten
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 278 13.4 reset noise canceller the figure 13.2 is the noise cancelle r diagram for noise cancel lation of reset. it has the noise cancellation value of about 2us (@v dd =5v) to the low input of system reset. figure 13.2 reset noise canceller timer diagram 13.5 power on reset when rising device power, the por (power on reset) has a function to reset the device. if por is used, it executes the device reset function instead of the reset ic or the reset circuits. figure 13.3 fast vdd rising time figure 13.4 internal reset release timing on power-up vdd npor (internal signal) internal resetb oscillation bit starts bit overflows slow vdd rise time, min. 0.15v/ms v por =1.4v (typ) vdd npor (internal signal) internal resetb oscillation bit starts bit overflows fast vdd rise time t > t rnc t > t rnc t > t rnc t < t rnc t < t rnc a a
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 279 figure 13.5 configuration timing when power-on figure 13.6 boot process waveform reset release config read por :vdd input :internal osc vdd internal npor pad resetb bit (for config) lvr_resetb bit (for reset) int-osc 8mhz/8 int-osc (8mhz) reset_sysb config read 1us x 256 x 28h = about 10ms 1us x 4096 x 4h = about 16ms 00 01 02 03 00 .. 27 28 f1 counting for config read start after por is released ?h? int-osc 8mhz / 8 = 1mhz (1us) 00 01 01 02 03 04 05 00
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 280 table 13-2 boot process description process description remarks -no operation -1st por level detection -about 1.4v - (int-osc 8mhz/8)x256x28h delay section (=10ms) -vdd input voltage must rise over than flash operating voltage for config read -slew rate 0.15v/ms - config read point -about 1.5v ~ 1.6v -config value is determined by writing option - rising section to reset release level -16ms point after por or ext_reset release - reset release section (bit overflow) i) after16ms, after external reset release (external reset) ii) 16ms point after por (por only) - bit is used for peripheral stability -normal operation
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 281 13.6 external resetb input the external resetb is the input to a schmitt trigger. if reset b pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. after reset state becomes ?1?, it n eeds the stabilization ti me with 16ms and after the stab le state, the internal reset becomes ?1?. the reset process step needs 5 oscillator clocks. and the program execution starts at the vector address stored at address 0000h. figure 13.7 timing diagram after reset figure 13.8 oscillator generating waveform example note) as shown figure 13.8, the stable generating time is not included in the start-up time. the resetb pin has a pull-up register by h/w. osc start timing prescaler count start vdd osc address bus core bus main program stabilization time tst = 16.4ms ? resetb release internal resetb release 1 2 3 4 5 ? 00 01 02 ? ? ? ? ? ? ? 02 reset process step
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 282 13.7 brown out detector processor the z51f3220 has an on-chip brown-out detection circuit (bod) for monitoring the vdd level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by lvrvs[3:0] bit to be 1.60v, 2.00v, 2.10v, 2.20v,2.32v, 2.44v, 2.59v, 2.75v, 2.93v, 3.14v, 3.38v, 3.67v, 4.00v, 4.40v. in the stop mode, this will contribute significantly to the total current consumption. so to minimize the current consumption, the lvren bit is set to off by software. figure 13.9 block diagram of bod figure 13.10 internal reset at the power fail situation vdd internal resetb vdd internal resetb v bod max v bod min 16ms t < 16ms 16ms v bod max v bod min lvrvs[3:0] reset_bodb brown out detector (bod) d q cp r external vdd lvren lvrf (low voltage reset flag) cpu write sclk (system clk) npor
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 283 figure 13.11 configuration timing when bod reset 13.8 lvi block diagram m u x lvif lvien 2.44v vdd lviref reference voltage generator 2.59v 2.75v lvi circuit lvils[3:0 ] 2.93v 3.14v 3.38v 3.67v 4.00v 4.40v 2.10v 2.20v 2.32v 2.00v 4 figure 13.12 lvi diagram vdd internal npor pad resetb bit (for config) lvr_resetb bit (for reset) int-osc 8mhz/8 int-osc (8mhz) reset_sysb config read 1us x 256 x 28h = about 10ms 1us x 4096 x 4h = about 16ms f1 00 01 02 00 .. .. .. 27 28 f1 ?h? int-osc 8mhz / 8 = 1mhz (1us) ?h? ?h? main osc off 01 02 03 04 00
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 284 13.8.1 register map table 13-3 reset operation register map name address dir default description rstfr e8h r/w 80h reset flag register lvrcr d8h r/w 00h low voltage reset control register lvicr 86h r/w 00h low voltage indicator control register 13.8.2 reset operation register description the reset control register consists of the reset flag register (rstfr), low voltage reset control register (lvrcr), and low voltage indicator control register (lvicr). 13.8.3 register description for reset operation rstfr (reset flag register) : e8h 7 6 5 4 3 2 1 0 porf extrf wdtrf ocdrf lvrf ? ? ? r/w r/w r/w r/w r/w ? ? ? initial value : 80h porf power-on reset flag bit. the bit is reset by writing ?0? to this bit. 0 no detection 1 detection extrf external reset (resetb) flag bit. the bi t is reset by writing ?0? to this bit or by power-on reset. 0 no detection 1 detection wdtrf watch dog reset flag bit. the bit is reset by writing ?0? to this bit or by power-on reset. 0 no detection 1 detection ocdrf on-chip debug reset flag bit. the bit is reset by writing ?0? to this bit or by power-on reset. 0 no detection 1 detection lvrf low voltage reset flag bit. the bit is reset by writing ?0? to this bit or by power-on reset. 0 no detection 1 detection notes) 1. when the power-on reset occurs, the porf bit is only set to ?1?, the other flag (wdtrf and ocdrf) bits are all cleared to ?0?. 2. when the power-on reset occurs, the extrf bit is unknown, at that time, the extrf bit can be set to ?1? when external reset (resetb) occurs. 3. when the power-on reset occurs, the lvrf bit is unknown, at that time, the lvrf bit can be set to ?1? when lvr reset occurs. 4. when a reset except the por occurs, the corresponding flag bit is only set to ?1?, the other flag bits are kept in the previous values.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 285 lvrcr (low voltage reset control register) : d8h 7 6 5 4 3 2 1 0 lvrst ? ? lvrvs3 lvrvs2 lvrvs1 lvrvs0 lvren r/w ? ? r/w r/w r/w r/w r/w initial value : 00h lvrst lvr enable when stop release 0 not effect at stop release 1 lvr enable at stop release notes) when this bit is ?1?, the lvren bit is cleared to ?0? by stop mode to release. (lvr enable) when this bit is ?0?, the lvren bit is not effect by stop mode to release. lvrvs[3:0] lvr voltage select lvrvs3 lvrvs2 lvrvs1 lvrvs0 description 0 0 0 0 1.60v 0 0 0 1 2.00v 0 0 1 0 2.10v 0 0 1 1 2.20v 0 1 0 0 2.32v 0 1 0 1 2.44v 0 1 1 0 2.59v 0 1 1 1 2.75v 1 0 0 0 2.93v 1 0 0 1 3.14v 1 0 1 0 3.38v 1 0 1 1 3.67v 1 1 0 0 4.00v 1 1 0 1 4.40v 1 1 1 0 not available 1 1 1 1 not available lvren lvr operation 0 lvr enable 1 lvr disable notes) 1. the lvrvs[3:0] bits are cleared by a power-on reset but are retained by other reset signals. 2. the lvrvs[3:0] bits should be set to ?0000b? while lvren bit is ?1?.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 286 lvicr (low voltage indicator control register) : 86h 7 6 5 4 3 2 1 0 ? ? lvif lvien lvils3 lvils2 lvils1 lvils0 ? ? r/w r/w r/w r/w r/w r/w initial value : 00h lvif low voltage indicator flag bit 0 no detection 1 detection lvien lvi enable/disable 0 disable 1 enable lvils[3:0] lvi level select lvils3 lvils2 lvils1 lvils0 description 0 0 0 0 2.00v 0 0 0 1 2.10v 0 0 1 0 2.20v 0 0 1 1 2.32v 0 1 0 0 2.44v 0 1 0 1 2.59v 0 1 1 0 2.75v 0 1 1 1 2.93v 1 0 0 0 3.14v 1 0 0 1 3.38v 1 0 1 0 3.67v 1 0 1 1 4.00v 1 1 0 0 4.40v other values not available
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 287 14. on-chip debug system 14.1 overview 14.1.1 description on-chip debug system (ocd) of z51f3220 can be used for programming the non-volatile memories and on- chip debugging. detail descriptions for programming via the ocd interface can be found in the following chapter. figure 14.1 shows a block diagram of the ocd interface and the on-chip debug system. 14.1.2 feature ? two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus ? debugger access to: ? all internal peripheral units ? internal data ram ? program counter ? flash and data eeprom memories ? extensive on-chip debug support for break conditions, including ? break instruction ? single step break ? program memory break points on single address ? programming of flash, eeprom, fuses, and lock bits through the two-wire interface ? on-chip debugging supported by dr.choice ? ? operating frequency supports the maximum frequency of the target mcu bdc format converter usb cpu code memor y - sram - flash - eeprom data memory dbg register peripheral user i/o a ddress bus internal data bus dsda dscl t arget mcu internal circuit dbg control
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 288 figure 14.1 block diagram of on-chip debug system 14.2 two-pin external interface 14.2.1 basic transmission packet ? 10-bit packet transmission using two-pin interface. ? 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. ? parity is even of ?1? for 8-bit data in transmitter. ? receiver generates acknowledge bit as ?0? when transmission for 8-bit data and its parity has no error. ? when transmitter has no acknowledge (acknowledge bit is ?1? at tenth clock), error process is executed in transmitter. ? when acknowledge error is generated, host pc makes stop condition and transmits command which has error again. ? background debugger command is composed of a bundle of packet. ? start condition and stop condition notify the start and the stop of background debugger command respectively. figure 14.2 10-bit transmission packet
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 289 14.2.2 packet transmission timing 14.2.2.1 data transfer figure 14.3 data transfer on the twin bus 14.2.2.2 bit transfer figure 14.4 bit transfer on the serial bus data line stable: data valid except start and stop change of data allowed dsd a dscl st sp start stop dsda dscl lsb acknowledgement signal from receive r a c k a ck 1 10 110 acknowledgement signal from receive r lsb
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 290 14.2.2.3 start and stop condition figure 14.5 start and stop condition 14.2.2.4 acknowledge bit figure 14.6 acknowledge on the serial bus 1 9 2 10 data output by transmitte r data output by receive r dscl from maste r clock pulse for acknowledgement no acknowledge acknowledge st sp start condition stop condition dsda dscl dsda dscl
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 291 figure 14.7 clock synchronization during wait procedure start wait start high host pc dscl out target device dscl out dscl wait high maximum 5 t sclk internal operation a cknowledge bit transmission minimum 1 t sclk for next byte transmission a cknowledge bit transmission minimum 500ns
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 292 14.2.3 connection of transmission two-pin interface connection uses open-drain (wire-and bidirectional i/o). figure 14.8 connection of transmission dsc l ou t dsd a ou t dsd a in dscl(debugger serial clock line) dsda(debugger serial data line) dsd a ou t dsd a in host machine(master) t arget device(slave) v dd v dd current source for dscl to fast 0 to 1 transition in high speed mode pull - up resistors r p r p vdd dsc l in dscl ou t dscl in
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 293 15. flash memory 15.1 overview 15.1.1 description z51f3220 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. the flash memory can be read by ?movc? instruction and it can be programmed in ocd, serial isp mode or user program mode. ? flash size : 32kbytes ? single power supply program and erase ? command interface for fast program and erase operation ? up to 100,000 program/erase cycles at typical voltage and temperature for flash memory
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 294 15.1.2 flash program rom structure sector 511 07fffh 07fc0h 07fbfh 07fc0h 07f80h flash sector address sector 510 07f80h 07f7fh 07f40h sector 509 07f40h 07f3fh sector 508 sector 2 00080h 0007fh 00040h sector 1 00040h 0003fh 00000h sector 0 00000h 00080h 8000h flash page buffer (external data memory, 64bytes) 803fh rom address accessed by movx instruction only page(sector) buffer address flash controller 64bytes fsadrh/m/l fidr fmcr figure 15.1 flash program rom structure
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 295 15.1.3 register map table 15-1flash memory register map name address dir default description fsadrh fah r/w 00h flash sector address high register fsadrm fbh r/w 00h flash sector address middle register fsadrl fch r/w 00h flash sector address low register fidr fdh r/w 00h flash identification register fmcr feh r/w 00h flash mode control register 15.1.4 register description for fl ash memory control and status flash control register consists of the flash sector address high register (fsadrh), flash sector address middle register (fsadrm), flash sector address low register (fsadrl), flash identification register (fidr), and flash mode control register (fmcr). they are mapped to sfr area and can be accessed only in programming mode.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 296 15.1.5 register description for flash fsadrh (flash sector address high register) : fah 7 6 5 4 3 2 1 0 ? ? ? ? fsadrh3 fsadrh 2 fsadrh1 fsadrh0 ? ? ? ? r/w r/w r/w r/w initial value : 00h fsadrh[3:0] flash sector address high fsadrm (flash sector address middle register) : fbh 7 6 5 4 3 2 1 0 fsadrm7 fsadrm6 fsadrm5 fsadrm4 fsadrm3 fsadrm2 fsadrm1 fsadrm0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h fsadrm[7:0] flash sector address middle fsadrl (flash sector address low register) : fch 7 6 5 4 3 2 1 0 fsadrl7 fsadrl6 fsadrl5 fsadrl4 fsadrl3 fsadrl2 fsadrl1 fsadrl0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h fsadrl[7:0] flash sector address low fidr (flash identification register) : fdh 7 6 5 4 3 2 1 0 fidr7 fidr6 fidr5 fidr4 fidr3 fidr2 fidr1 fidr0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 00h fidr[7:0] flash identification others no identification value 10100101 identification value for a flash mode (these bits are automatically cleared to logic ?00h? immediately after one time operation)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 297 fmcr (flash mode cont rol register) : feh 7 6 5 4 3 2 1 0 fmbusy ? ? ? ? fmcr2 fmcr1 fmcr0 r ? ? ? ? r/w r/w r/w initial value : 00h fmbusy flash mode busy bit. this bit will be used for only debugger. 0 no effect when ?1? is written 1 busy fmcr[2:0] flash mode control bits. during a flash mode operation, the cpu is hold and the global interrupt is on disable state regardless of the ie.7 (ea) bit. fmcr2 fmcr1 fmcr0 description 0 0 1 select flash page buffer reset mode and start regardless of the fidr value (clear all 64bytes to ?0?) 0 1 0 select flash sector erase mode and start operation when the fidr=?10100101b? 0 1 1 select flash sector write mode and start operation when the fidr=?10100101b? 1 0 0 select flash sector hard lock and start operation when the fidr=?10100101b? others values: no operation (these bits are automatically cleared to logic ?00h? immediately after one time operation)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 298 15.1.6 serial in-system program (isp) mode serial in-system program uses the interface of debugger which uses two wires. refer to chapter 14 in details about debugger 15.1.7 protection area (user program mode) z51f3220 can program its own flash memory (protection area). the protection area can not be erased or programmed. the protection areas are available only when the paen bit is cleared to ?0?, that is, enable protection area at the configure option 2 if it is needed. if the protection ar ea isn?t enabled (paen =?1?), this area can be used as a normal program memory. the size of protection area can be varied by setting of configure option 2. table 15-2 protection area size protection area size select size of protection area address of protection area pass1 pass0 0 0 3.8k bytes 0100h ? 0fffh 0 1 1.7k bytes 0100h ? 07ffh 1 0 768 bytes 0100h ? 03ffh 1 1 256 bytes 0100h ? 01ffh note) refer to chapter 16 in configure option control.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 299 15.1.8 erase mode the sector erase program procedure in user program mode 1. page buffer clear (fmcr=0x01) 2. write ?0? to page buffer 3. set flash sector address register (fsadrh/fsadrm/fsadrl). 4. set flash identification register (fidr). 5. set flash mode control register (fmcr). 6. erase verify program tip C sector erase mov fmcr,#0x01 ;page buffer clear nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 mov r0,#64 ;sector size is 64bytes mov dph,#0x80 mov dpl,#0 pgbuf_clr: movx @dptr,a inc dptr djnz r0, pgbuf_clr ;write 0 to all page buffer mov fsadrh,#0x00 mov fsadrm,#0x7f mov fsadrl,#0x40 ;select sector 509 mov fidr,#0xa5 ;identification value mov fmcr,#0x02 ;start flash erase mode nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 ;erase verify mov r0,#64 ;sector size is 64bytes mov r1,#0 mov dph,#0x7f mov dpl,#0x40 erase_verify: movc a,@a+dptr subb a,r1 jnz verify_error inc dptr djnz r0, erase_verify verify_error:
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 300 the byte erase program procedure in user program mode 1. page buffer clear (fmcr=0x01) 2. write ?0? to page buffer 3. set flash sector address register (fsadrh/fsadrm/fsadrl). 4. set flash identification register (fidr). 5. set flash mode control register (fmcr). 6. erase verify program tip C byte erase mov fmcr,#0x01 ;page buffer clear nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 mov dph,#0x80 mov dpl,#0 movx @dptr,a mov dph,#0x80 mov dpl,#0x05 movx @dptr,a ;write 0 to page buffer mov fsadrh,#0x00 mov fsadrm,#0x7f mov fsadrl,#0x40 ;select sector 509 mov fidr,#0xa5 ;identification value mov fmcr,#0x02 ;start flash erase mode nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 ;erase verify mov r1,#0 mov dph,#0x7f mov dpl,#0x40 movc a,@a+dptr subb a,r1 ;0x7f40 = 0 ? jnz verify_error mov a,#0 mov r1,#0 mov dph,#0x7f mov dpl,#0x45 movc a,@a+dptr subb a,r1 ;0x7f45 = 0 ? jnz verify_error verify_error:
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 301 15.1.9 write mode the sector write program procedure in user program mode 1. page buffer clear (fmcr=0x01) 2. write data to page buffer 3. set flash sector address re gister (fsadrh/fsadrm/fsadrl). 4. set flash identification register (fidr). 5. set flash mode control register (fmcr). 6. erase verify program tip C sector write mov fmcr,#0x01 ;page buffer clear nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 mov r0,#64 ;sector size is 64bytes mov dph,#0x80 mov dpl,#0 pgbuf_wr: movx @dptr,a inc a inc dptr djnz r0, pgbuf_wr ;write data to all page buffer mov fsadrh,#0x00 mov fsadrm,#0x7f mov fsadrl,#0x40 ;select sector 509 mov fidr,#0xa5 ;identification value mov fmcr,#0x03 ;start flash write mode nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 ;write verify mov r0,#64 ;sector size is 64bytes mov r1,#0 mov dph,#0x7f mov dpl,#0x40 write_verify: movc a,@a+dptr subb a,r1 jnz verify_error inc r1 inc dptr djnz r0, write_verify verify_error:
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 302 the byte write program procedure in user program mode 1. page buffer clear (fmcr=0x01) 2. write data to page buffer 3. set flash sector address re gister (fsadrh/fsadrm/fsadrl). 4. set flash identification register (fidr). 5. set flash mode control register (fmcr). 6. erase verify program tip C byte write mov fmcr,#0x01 ;page buffer clear nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#5 mov dph,#0x80 mov dpl,#0 movx @dptr,a ;write data to page buffer mov a,#6 mov dph,#0x80 mov dpl,#0x05 movx @dptr,a ;write data to page buffer mov fsadrh,#0x00 mov fsadrm,#0x7f mov fsadrl,#0x40 ;select sector 509 mov fidr,#0xa5 ;identification value mov fmcr,#0x03 ;start flash write mode nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. mov a,#0 ;write verify mov r1,#5 mov dph,#0x7f mov dpl,#0x40 movc a,@a+dptr subb a,r1 ;0x7f40 = 5 ? jnz verify_error mov a,#0 mov r1,#6 mov dph,#0x7f mov dpl,#0x45 movc a,@a+dptr subb a,r1 ;0x7f45 = 6 ? jnz verify_error verify_error:
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 303 15.1.10 read mode the reading program procedure in user program mode 1. load receive data from flash memory on movc instruction by indirectly addressing mode. program tip C reading mov a,#0 mov dph,#0x7f mov dpl,#0x40 ;flash memory address movc a,@a+dptr ;read data from flash memory 15.1.11 hard lock mode the reading program procedure in user program mode 1. set flash identification register (fidr). 2. set flash mode control register (fmcr). program tip C reading mov fidr,#0xa5 ;identification value mov fmcr,#0x04 ;start flash hard lock mode nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed. nop ;dummy instruction, this instruction must be needed.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 304 16. configure option 16.1 configure option control the data for configure option should be written in the configure option area (003eh ? 003fh) by programmer (writer tools). configure option 1 : rom address 003fh 7 6 5 4 3 2 1 0 r_p hl ? ? ? ? ? rsts initial value : 00h r_p read protection 0 disable ?read protection? 1 enable ?read protection? hl hard-lock 0 disable ?hard-lock? 1 enable ?hard-lock? rsts resetb select 0 p55 port 1 resetb port with a pull-up resistor configure option 2: rom address 003eh 7 6 5 4 3 2 1 0 ? ? ? ? ? paen pass1 pass0 initial value : 00h paen protection area enable/disable 0 disable protection (erasable by instruction) 1 enable protection (not erasable by instruction) pass [1:0] protection area size select pass1 pass0 description 0 0 3.8k bytes (address 0100h ? 0fffh) 0 1 1.7k bytes (address 0100h ? 07ffh) 1 0 768 bytes (address 0100h ? 03ffh) 1 1 256 bytes (address 0100h ? 01ffh)
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 305 17. appendix a. instruction table instructions are either 1, 2 or 3 bytes long as listed in the ?bytes? column below. each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles. arithmetic mnemonic description bytes cycles hex code add a,rn add register to a 1 1 28-2f add a,dir add direct byte to a 2 1 25 add a,@ri add indirect memory to a 1 1 26-27 add a,#data add immediate to a 2 1 24 addc a,rn add register to a with carry 1 1 38-3f addc a,dir add direct byte to a with carry 2 1 35 addc a,@ri add indirect memory to a with carry 1 1 36-37 addc a,#data add immediate to a with carry 2 1 34 subb a,rn subtract register from a with borrow 1 1 98-9f subb a,dir subtract direct byte from a with borrow 2 1 95 subb a,@ri subtract indirect memory from a with borrow 1 1 96-97 subb a,#data subtract immediate from a with borrow 2 1 94 inc a increment a 1 1 04 inc rn increment register 1 1 08-0f inc dir increment direct byte 2 1 05 inc @ri increment indirect memory 1 1 06-07 dec a decrement a 1 1 14 dec rn decrement register 1 1 18-1f dec dir decrement direct byte 2 1 15 dec @ri decrement indirect memory 1 1 16-17 inc dptr increment data pointer 1 2 a3 mul ab multiply a by b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust a 1 1 d4 logical mnemonic description bytes cycles hex code anl a,rn and register to a 1 1 58-5f anl a,dir and direct byte to a 2 1 55 anl a,@ri and indirect memory to a 1 1 56-57 anl a,#data and immediate to a 2 1 54 anl dir,a and a to direct byte 2 1 52 anl dir,#data and immediate to direct byte 3 2 53 orl a,rn or register to a 1 1 48-4f orl a,dir or direct byte to a 2 1 45 orl a,@ri or indirect memory to a 1 1 46-47 orl a,#data or immediate to a 2 1 44 orl dir,a or a to direct byte 2 1 42 orl dir,#data or immediate to direct byte 3 2 43 xrl a,rn exclusive-or register to a 1 1 68-6f xrl a,dir exclusive-or direct byte to a 2 1 65 xrl a, @ri exclusive-or indirect memory to a 1 1 66-67
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 306 xrl a,#data exclusive-or immediate to a 2 1 64 xrl dir,a exclusive-or a to direct byte 2 1 62 xrl dir,#data exclusive-or immediate to direct byte 3 2 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 swap a swap nibbles of a 1 1 c4 rl a rotate a left 1 1 23 rlc a rotate a left through carry 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through carry 1 1 13 data transfer mnemonic description bytes cycles hex code mov a,rn move register to a 1 1 e8-ef mov a,dir move direct byte to a 2 1 e5 mov a,@ri move indirect memory to a 1 1 e6-e7 mov a,#data move immediate to a 2 1 74 mov rn,a move a to register 1 1 f8-ff mov rn,dir move direct byte to register 2 2 a8-af mov rn,#data move immediate to register 2 1 78-7f mov dir,a move a to direct byte 2 1 f5 mov dir,rn move register to direct byte 2 2 88-8f mov dir,dir move direct byte to direct byte 3 2 85 mov dir,@ri move indirect memory to direct byte 2 2 86-87 mov dir,#data move immediate to direct byte 3 2 75 mov @ri,a move a to indirect memory 1 1 f6-f7 mov @ri,dir move direct byte to indirect memory 2 2 a6-a7 mov @ri,#data move immediate to indirect memory 2 1 76-77 mov dptr,#data move immediate to data pointer 3 2 90 movc a,@a+dptr move code byte relative dptr to a 1 2 93 movc a,@a+pc move code byte relative pc to a 1 2 83 movx a,@ri move external data(a8) to a 1 2 e2-e3 movx a,@dptr move external data(a16) to a 1 2 e0 movx @ri,a move a to external data(a8) 1 2 f2-f3 movx @dptr,a move a to external data(a16) 1 2 f0 push dir push direct byte onto stack 2 2 c0 pop dir pop direct byte from stack 2 2 d0 xch a,rn exchange a and register 1 1 c8-cf xch a,dir exchange a and direct byte 2 1 c5 xch a,@ri exchange a and indirect memory 1 1 c6-c7 xchd a,@ri exchange a and indirect memory nibble 1 1 d6-d7 boolean mnemonic description bytes cycles hex code clr c clear carry 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry 2 2 82 anl c,/bit and direct bit inverse to carry 2 2 b0
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 307 orl c,bit or direct bit to carry 2 2 72 orl c,/bit or direct bit inverse to carry 2 2 a0 mov c,bit move direct bit to carry 2 1 a2 mov bit,c move carry to direct bit 2 2 92 branching mnemonic description bytes cycles hex code acall addr 11 absolute jump to subroutine 2 2 11f1 lcall addr 16 long jump to subroutine 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr 11 absolute jump unconditional 2 2 01 e1 ljmp addr 16 long jump unconditional 3 2 02 sjmp rel short jump (relative address) 2 2 80 jc rel jump on carry = 1 2 2 40 jnc rel jump on carry = 0 2 2 50 jb bit,rel jump on direct bit = 1 3 2 20 jnb bit,rel jump on direct bit = 0 3 2 30 jbc bit,rel jump on direct bit = 1 and clear 3 2 10 jmp @a+dptr jump indirect relative dptr 1 2 73 jz rel jump on accumulator = 0 2 2 60 jnz rel jump on accumulator 0 2 2 70 cjne a,dir,rel compare a,direct jne relative 3 2 b5 cjne a,#d,rel compare a,immediate jne relative 3 2 b4 cjne rn,#d,rel compare register, immediate jne relative 3 2 b8-bf cjne @ri,#d,rel compare indirect, immediate jne relative 3 2 b6-b7 djnz rn,rel decrement register, jnz relative 3 2 d8-df djnz dir,rel decrement direct byte, jnz relative 3 2 d5 miscellaneous mnemonic description bytes cycles hex code nop no operation 1 1 00 additional instructions (selected through eo[7:4]) mnemonic description bytes cycles hex code movc @(dptr++),a m8051w/m8051ew-specific instruction supporting software download into program memory 1 2 a5 trap software break command 1 1 a5 in the above table, an entry such as e8-ef indicates a continuous block of hex opcodes used for 8 different registers, the register numbers of which are defined by the lowest three bits of the corresponding code. non- continuous blocks of codes, shown as 11 f1 (for example), are used for absolute jumps and calls, with the top 3 bits of the code being used to store the top three bits of the destination address. the cjne instructions use the abbreviation #d for immediate data; other instructions use #data.
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 308 b. instructions on how to use the input port. ? error occur status ? using compare jump instructions with input port, it could cause error due to the timing conflict inside the mcu. ? compare jump instructions which cause potential error used with input port condition: jb bit, rel ; jump on direct bit=1 jnb bit, rel ; jump on direct bit=0 jbc bit, rel ; jump on direct bit=1 and clear cjne a, dir, rel ; compare a, direct jne relative djnz dir, rel ; decrement direct byte, jnz relative ? it is only related with input port. internal parameters, sfrs and output bit ports don?t cause any error by using compare jump instructions. ? if input signal is fixed, there is no error in using compare jump instructions. ? error status example ? preventative measures (2 cases) ? do not use input bit port for bit operation but for byte operation. using byte operation instead of bit oper ation will not cause any error in using compare jump instructions for input port. while(1){ if (p00==1) { p10=1; } else { p10=0; } p11^=1; } zzz: jnb 080.0, xxx ; it possible to be error setb 088.0 sjmp yyy xxx: clr 088.0 yyy: mov c,088.1 cpl c mov 088.1,c sjmp zzz unsigned char re t_bit_err(void) { return !p00 ; } mov r7, #000 jb 080.0, xxx ; it possible to be error mov r7, #001 xxx: ret while(1){ if ((p0&0x01)==0x01) { p10=1; } else { p10=0; } p11^=1; } zzz: mov a, 080 ; read as byte jnb 0e0.0, xxx ; compare setb 088.0 sjmp yyy xxx: clr 088.0 yyy: mov c,088.1 cpl c mov 088.1,c sjmp zzz
z51f3220 product specification ps029902-0212 p r e l i m i n a r y 309 ? if you use input bit port for compare jump instruction, you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction. bit tt; while(1){ tt=p00; if (tt==0){ p10=1;} else {p10=0;} p11^=1; } zzz: mov c,080.0 ; input port use internal parameter mov 020.0, c ; move jb 020.0, xxx ; compare setb 088.0 sjmp yyy xxx: clr 088.0 yyy: mov c,088.1 cpl c mov 088.1,c sjmp zzz
ps029902-0212 p r e l i m i n a r y customer support z51f3220 product specification 310 customer support to share comments, get your technical questio ns answered, or report issues you may be experiencing with our products, please visit zilog?s technical support page at ? http://support.zilog.com . to learn more about this product, find additional documentation, or to discover other fac- ets about zilog product offerings, please visit the zilog knowledge base or consider par- ticipating in the zilog forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .

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